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US-12621974-B2 - Static random access memory and its layout pattern

US12621974B2US 12621974 B2US12621974 B2US 12621974B2US-12621974-B2

Abstract

The invention provides a layout pattern of static random access memory, which comprises a plurality of fin structures on a substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate. The transistors include a first pull-up transistor (PU 1 ), a first pull-down transistor (PD 1 ), a second pull-up transistor (PU 2 ) and a second pull-down transistor (PD 2 ), a first access transistor (PG 1 ), a second access transistor (PG 2 ), a first read port transistor (RPD) and a second read port transistor (RPG). The gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD 1 ), wherein a drain of the first pull-down transistor (PD 1 ) is connected to a first voltage source Vss 1 , and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss 2.

Inventors

  • Shu-Wei Yeh
  • Chang-Hung CHEN

Assignees

  • UNITED MICROELECTRONICS CORP.

Dates

Publication Date
20260505
Application Date
20221127
Priority Date
20221028

Claims (13)

  1. 1 . A layout pattern of static random access memory (SRAM), at least comprising: a substrate; a plurality of fin structures positioned on the substrate; a plurality of gate structures located on the substrate and span the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein each transistor includes a part of the gate structure spans a part of the fin structure, wherein the transistors include: a first pull-up transistor (PU 1 ), a first pull-down transistor (PD 1 ), a second pull-up transistor (PU 2 ) and a second pull-down transistor (PD 2 ) form a latch circuit; a first access transistor (PG 1 ) and a second access transistor (PG 2 ) connected to the latch circuit; and a first read port transistor (RPD) and a second read port transistor (RPG) connected in series, wherein the gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD 1 ), and wherein the first pull-down transistor (PD 1 ) is disposed between the first pull-up transistor (PU 1 ) and the first read port transistor (RPD); wherein a drain of the first pull-down transistor (PD 1 ) is connected to a first voltage source Vss 1 , and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss 2 , wherein the gate of the first read port transistor (RPD) directly contacts the gate of the first pull-up transistor (PU 1 ) and the gate of the first pull-down transistor (PD 1 ), wherein the first voltage source Vss 1 is connected to a first metal layer, and the second voltage source Vss 2 is connected to a second metal layer, wherein the first metal layer is not in direct contact with the second metal layer.
  2. 2 . The layout pattern of static random access memory according to claim 1 , wherein the fin structures are arranged along a first direction and the gate structures are arranged along a second direction, and the first direction and the second direction are perpendicular to each other.
  3. 3 . The layout pattern of static random access memory according to claim 2 , wherein the first read port transistor (RPD), the first pull-up transistor (PU 1 ), the first pull-down transistor (PD 1 ) and the second access transistor (PG 2 ) are arranged along the second direction.
  4. 4 . The layout pattern of static random access memory according to claim 2 , wherein the second read port transistor (RPG), the second pull-up transistor (PU 2 ), the second pull-down transistor (PD 2 ) and the first access transistor (PG 1 ) are arranged along the second direction.
  5. 5 . The layout pattern of static random access memory according to claim 2 , wherein the first voltage source Vssl and the second voltage source Vss 2 are not electrically connected to each other.
  6. 6 . The layout pattern of static random access memory according to claim 5 , wherein the first metal layer and the second metal layer are aligned along the second direction.
  7. 7 . The layout pattern of static random access memory according to claim 6 , wherein the first read port transistor (RPD) and the second read port transistor (RPG) are aligned along the first direction.
  8. 8 . The layout pattern of static random access memory according to claim 6 , wherein the first metal layer includes a first contact plug, and the second metal layer includes a second contact plug.
  9. 9 . A static random access memory, at least comprising: a plurality of transistors distributed on a substrate, wherein the plurality of transistors comprising: a first pull-up transistor (PU 1 ), a first pull-down transistor (PD 1 ), a second pull-up transistor (PU 2 ) and a second pull-down transistor (PD 2 ) form a latch circuit; a first access transistor (PG 1 ) and a second access transistor (PG 2 ) connected to the latch circuit; and a first read port transistor (RPD) and a second read port transistor (RPG) connected in series, wherein the gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD 1 ), and wherein the first pull-down transistor (PD 1 ) is disposed between the first pull-up transistor (PU 1 ) and the first read port transistor (RPD); wherein a drain of the first pull-down transistor (PD 1 ) and a drain of the second pull-down transistor (PD 2 ) are connected to a first voltage source Vss 1 , and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss 2 , wherein the gate of the first read port transistor (RPD) directly contacts the gate of the first pull-up transistor (PU 1 ) and the gate of the first pull-down transistor (PD 1 ), wherein the first voltage source Vss 1 is connected to a first metal layer, and the second voltage source Vss 2 is connected to a second metal layer, wherein the first metal layer is not in direct contact with the second metal layer.
  10. 10 . The static random access memory according to claim 9 , wherein the first voltage source Vss 1 and the second voltage source Vss 2 are not electrically connected to each other.
  11. 11 . The static random access memory according to claim 9 , wherein a source of the second read port transistor (RPG) is connected to a read bit line (RBL).
  12. 12 . The static random access memory according to claim 9 , wherein a gate of the second read port transistor (RPG) is connected to a read word line (RWL).
  13. 13 . The static random access memory according to claim 9 , wherein a source of the first pull-up transistor (PU 1 ) and a source of the second pull-up transistor (PU 2 ) are connected to a third voltage source Vcc.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static random access memory (SRAM), in particular to a layout pattern of SRAM with high reading rate and high stability. 2. Description of the Prior Art An embedded static random access memory (SRAM) comprises a logic circuit and a static random access memory connected to the logic circuit. SRAM is a kind of volatile memory cell, which means it preserves data only while power is continuously applied. SRAM is built of cross-coupled inverters that store data during the time that power remains applied, unlike dynamic random access memory (DRAM) that needs to be periodically refreshed. Because of its high access speed, SRAM is also used in computer systems as a cache memory. SUMMARY OF THE INVENTION The invention provides a layout pattern of static random access memory, which at least comprises a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the plurality of fin structures, so as to form a plurality of transistors distributed on the substrate, wherein each transistor comprises a part of the gate structures spanning the part of the fin structures, and the plurality of transistors comprise: a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2) together form a latch circuit, a first access transistor (PG1) and a second access transistor (PG2) are connected to the latch circuit, and a first read port transistor (RPD) and a second read port transistor (RPG) connected in series, wherein the gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1), wherein a drain of the first pull-down transistor (PD1) is connected to a first voltage source, and a drain of the first read port transistor (RPD) is connected to a second voltage source. The present invention also provides a static random access memory, which at least comprises a plurality of transistors distributed on a substrate, wherein the plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2) and a second pull-down transistor (PD2) to form a latch circuit. a first access transistor (PG1) and a second access transistor (PG2) connected to the latch circuit, and a first read port transistor (RPD) and a second read port transistor (RPG) connected in series, wherein the gate structure of the first read port transistor (RPD) is connected to the gate structure of the first pull-down transistor (PD1), wherein a drain of the first pull-down transistor (PD1) and a drain of the second pull-down transistor (PD2) are connected to a first voltage source Vss1, and a drain of the first read port transistor (RPD) is connected to a second voltage source Vss2. The present invention is characterized in that, in conventional SRAM, a drain of the first pull-down transistor (PD1), a drain of the second pull-down transistor (PD2) and a drain of the first read port transistor (RPD) are commonly connected to a voltage source (Vss). However, in the present invention, a drain of the first pull-down transistor (PD1) and a drain of the second pull-down transistor (PD2) are connected to a first voltage source (Vss1), and a drain of the first read port transistor (RPD) is connected to a second voltage source (Vss2), that is, the first voltage source Vss1 and the second voltage source Vss2 are independent of each other. When the reading state is performed, the voltage of Vss2 can be independently lowered (for example, to a negative potential), which can increase the reading speed without affecting the stability of the latch circuit. On the other hand, when the SRAM is on standby state, it is also possible to increase the voltage of Vss2 (for example, to a positive potential), which can reduce the occurrence probability of leakage current and improve the stability of SRAM. The invention has the advantages of improving the quality and stability of components, and being compatible with the existing manufacturing process. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a SRAM memory cell in a SRAM according to the first embodiment of the present invention. FIG. 2 is a layout diagram of a static random access memory according to the first preferred embodiment of the present invention. FIG. 3 is a layout diagram of the SRAM of FIG. 2 after the first metal layer M1 is formed. FIG. 4 is a timing chart showing the operation of the 8TRF-SRAM memory cell of the present invention. DETAILED DESCRIPTION To provide a better understanding of the pre