US-12621975-B2 - Static random access memory with pre-charge circuit

Abstract

The present disclosure describes embodiments of a memory device with a pre-charge circuit. The memory device can include a memory cell, and the pre-charge circuit can include a first transistor and a second transistor. The first transistor includes a first gate terminal, a first source/drain (S/D) terminal coupled to a reference voltage, and a second S/D terminal coupled to a first terminal of the memory cell. The second transistor includes a second gate terminal, a third S/D terminal coupled to the reference voltage, and a fourth S/D terminal coupled to the second terminal of the memory cell. The first and second transistors are configured to pass the reference voltage in response to the control signal being applied to the first and second gate terminals, respectively.

Inventors

• PO-SHENG WANG
• Yangsyu Lin
• Cheng Hung Lee

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260505

Application Date

20230809

Claims (20)

1. 1 . A memory device, comprising: an array of memory cells comprising a first memory cell and a second memory cell, wherein each of the first and second memory cells comprises a first bitline and a second bitline; and a pre-charge circuit coupled to the array of memory cells and comprising a first pre-charge cell and a second pre-charge cell, wherein: the first pre-charge cell is configured to pass a power supply voltage to the first and second bitlines of the first memory cell based on a first control signal; and the second pre-charge cell is configured to pass the power supply voltage to the first and second bitlines of the second memory cell based on a second control signal, wherein the first pre-charge cell comprises: a first transistor with: a first gate terminal coupled to the first control signal; a first source/drain (S/D) terminal coupled to the power supply voltage; and a second S/D terminal, wherein the first transistor is configured to pass the power supply voltage from the first S/D terminal to the second S/D terminal; a second transistor with: a second gate terminal coupled to the first control signal; a third S/D terminal coupled to the power supply voltage; and a fourth S/D terminal, wherein the second transistor is configured to pass the power supply voltage from the third S/D terminal to the fourth S/D terminal; a first pass transistor with a third gate terminal coupled to the first control signal; and a second pass transistor with a fourth gate terminal coupled to the first control signal, wherein the first transistor, the second transistor, the first pass transistor, and the second pass transistor are the same transistor type.
2. 2 . The memory device of claim 1 , wherein the first pre-charge cell, the second pre-charge cell, and the array of memory cells are arranged in rows and columns, and wherein: the first pre-charge cell and the second-pre-charge cell are located in a first row and in first and second columns, respectively; and the first and second memory cells are located in a second row below the first row and in the first and second columns, respectively.
3. 3 . The memory device of claim 1 , wherein the pre-charge circuit further comprises: a third pre-charge cell coupled to the first pre-charge cell and configured to pass the power supply voltage to the first and second bitlines of the first memory cell based on the first control signal; and a fourth pre-charge cell coupled to the second pre-charge cell and configured to pass the power supply voltage to the first and second bitlines of the second memory cell based on the second control signal; wherein the first pre-charge cell, the second pre-charge cell, the third pre-charge cell, and the fourth pre-charge cell, and the array of memory cells are arranged in rows and columns, and wherein: the first pre-charge cell and the second-pre-charge cell are located in a first row and in first and second columns, respectively; the third pre-charge cell and the fourth pre-charge cell are located in a second row below the first row and in the first and second columns, respectively; and the first and second memory cells are located in a third row below the second row and in the first and second columns, respectively.
4. 4 . The memory device of claim 1 , wherein the pre-charge circuit further comprises: a third pre-charge cell coupled to the first pre-charge cell and configured to pass the power supply voltage to the first and second bitlines of the first memory cell based on the first control signal; and one or more write assist cells coupled to the first and third pre-charge cells.
5. 5 . The memory device of claim 1 , wherein the first pre-charge cell further comprises a third transistor with a third gate terminal, a fifth S/D terminal connected to the second S/D terminal, and a sixth S/D terminal connected to the first bitline of the first or second memory cell.
6. 6 . The memory device of claim 1 , wherein the second S/D terminal of the first pre-charge cell is connected to the first bitline of the first or second memory cell.
7. 7 . The memory device of claim 1 , wherein the first pre-charge cell further comprises one or more write assist circuits coupled to the first and second bitlines of the first memory cell.
8. 8 . The memory device of claim 1 , further comprising: a first power supply configured to provide a power supply to the array of memory cells.
9. 9 . A device, comprising: an array of memory cells comprising a plurality of memory cells, wherein each of the plurality of memory cells comprises a bitline pair; and a pre-charge circuit coupled to the array of memory cells and comprising a plurality of pre-charge cells, wherein each of the plurality of pre-charge cells comprises a plurality of transistors configured to pass a power supply voltage to the bitline pair of each of the plurality of memory cells based on a pre-charge control signal, wherein each of the pre-charge cells comprises: a first transistor comprising a first gate terminal; a second transistor comprising a second gate terminal; a first pass transistor comprising a third gate terminal, wherein the first pass transistor is configured to pass the power supply voltage from the first transistor to a first bitline of the bitline pair; and a second pass transistor comprising a fourth gate terminal, wherein the second pass transistor is configured to pass the power supply voltage from the second transistor to a second bitline of the bitline pair, wherein the first gate terminal, the second gate terminal, the third gate terminal, and the fourth gate terminal are coupled to the pre-charge control signal, and wherein the first transistor, the second transistor, the first pass transistor, and the second pass transistor are the same transistor type.
10. 10 . The device of claim 9 , wherein the first transistor further comprises: a first source/drain (S/D) terminal coupled to the power supply voltage; and a second S/D terminal coupled to the first bitline of the bitline pair, wherein the first transistor is configured to pass the power supply voltage from the first S/D terminal to the second S/D terminal; and the second transistor further comprises: a third S/D terminal coupled to the power supply voltage; and a fourth S/D terminal coupled to the second bitline of the bitline pair, wherein the second transistor is configured to pass the power supply voltage from the third S/D terminal to the fourth S/D terminal.
11. 11 . The device of claim 9 , wherein memory cells in the array of memory cells are arranged in rows and columns, and wherein the plurality of pre-charge cells are located in a first row and one or more of the memory cells in the array of memory cells are located in a second row below the first row.
12. 12 . The device of claim 11 , wherein a first pre-charge cell and a second pre-charge cell of the plurality of pre-charge cells are coupled to one another along a column in the array of memory cells and configured to pass the power supply voltage based on the pre-charge control signal.
13. 13 . The device of claim 12 , wherein a third pre-charge cell and a fourth pre-charge cell of the plurality of pre-charge cells are coupled to one another along another column in the array of memory cells and configured to pass the power supply voltage based on another pre-charge control signal.
14. 14 . The device of claim 9 , wherein one or more of the plurality of pre-charge cells comprise one or more write assist circuits.
15. 15 . A device, comprising: an array of memory cells comprising a first memory cell and a second memory cell; and a pre-charge circuit coupled to the array of memory cells and comprising a first pre-charge cell and a second pre-charge cell, wherein: the first pre-charge cell is configured to pass a power supply voltage to the first memory cell based on a first pre-charge control signal; and the second pre-charge cell is configured to pass the power supply voltage to the second memory cell based on a second pre-charge control signal, wherein each of the first and second pre-charge cells comprises: a first transistor comprising a first gate terminal; a second transistor comprising a second gate terminal; a first pass transistor comprising a third gate terminal, wherein the first pass transistor is configured to pass the power supply voltage from the first transistor to the first memory cell or the second memory cell; and a second pass transistor comprising a fourth gate terminal, wherein the second pass transistor is configured to pass the power supply voltage from the second transistor to the first memory cell or the second memory cell, wherein the first gate terminal, the second gate terminal, the third gate terminal, and the fourth gate terminal are coupled to a common signal, wherein the common signal is the first pre-charge control signal or the second pre-charge control signal, and wherein the first transistor, the second transistor, the first pass transistor, and the second pass transistor are the same transistor type.
16. 16 . The device of claim 15 , wherein the first transistor further comprises: a first source/drain (S/D) terminal coupled to the power supply voltage; and a second S/D terminal coupled to the first or second memory cell, wherein the first transistor is configured to pass the power supply voltage from the first S/D terminal to the second S/D terminal; and the second transistor further comprises: a third S/D terminal coupled to the power supply voltage; and a fourth S/D terminal coupled to the first or second memory cell, wherein the second transistor is configured to pass the power supply voltage from the third S/D terminal to the fourth S/D terminal.
17. 17 . The device of claim 15 , wherein memory cells in the array of memory cells are arranged in rows and columns, and wherein the first and second pre-charge cells are located in a first row and one or more of the memory cells in the array of memory cells are located in a second row below the first row.
18. 18 . The device of claim 17 , wherein the pre-charge circuit further comprises a third pre-charge cell, and wherein the first pre-charge cell and the third pre-charge cell are coupled to one another along a column in the array of memory cells and configured to pass the power supply voltage to the first memory cell based on the first pre-charge control signal.
19. 19 . The device of claim 18 , wherein the pre-charge circuit further comprises a fourth pre-charge cell, and wherein the second pre-charge cell and the fourth pre-charge cell are coupled to one another along another column in the array of memory cells and configured to pass the power supply voltage to the second memory cell based on the second pre-charge control signal.
20. 20 . The device of claim 15 , wherein one or more of the first pre-charge cell and the second pre-charge cell comprise one or more write assist circuits.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a divisional of U.S. patent application Ser. No. 17/125,688, titled “Static Random Access Memory with Pre-Charge Circuit” and filed on Dec. 17, 2020, which claims the benefit of U.S. Provisional Patent Application No. 63/078,040, titled “Static Random Access Memory with Pre-Charge Circuit” and filed on Sep. 14, 2020. Both applications are incorporated herein by reference in their entireties. BACKGROUND Static random access memory (SRAM) is a type of semiconductor memory used in computing applications that require, for example, high-speed data access. For example, cache memory applications use SRAM to store frequently-accessed data—e.g., data accessed by a central processing unit. The SRAM's cell structure and architecture enable high-speed data access. The SRAM cell can include a bi-stable flip-flop structure with, for example, four to ten transistors. An SRAM architecture can include one or more arrays of memory cells and support circuitry. Each of the SRAM arrays is arranged in rows and columns called “wordlines” and “bitlines,” respectively. The support circuitry includes address and driver circuits to access each of the SRAM cells-via the wordlines and bitlines—for various SRAM operations. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is an illustration of a static random access memory with a pre-charge circuit, according to some embodiments of the present disclosure. FIG. 2 is an illustration of an example static random access memory circuit topology. FIG. 3 is an illustration of a first pre-charge cell topology, according to some embodiments of the present disclosure. FIGS. 4A and 4B are illustrations of a second pre-charge cell topology and associated layout, respectively, according to some embodiments of the present disclosure. FIGS. 5A and 5B are illustrations of a third pre-charge cell topology and associated layout, respectively, according to some embodiments of the present disclosure. FIG. 6 is an illustration of a fourth pre-charge cell topology, according to some embodiments of the present disclosure. FIG. 7 is an illustration of a fifth pre-charge cell topology, according to some embodiments of the present disclosure. FIG. 8 is an illustration of a first pre-charge circuit architecture with multiple pre-charge cells and a write assist cell, according to some embodiments of the present disclosure. FIG. 9 is an illustration of a second pre-charge circuit architecture with multiple pre-charge cells and multiple write assist cells, according to some embodiments of the present disclosure. FIG. 10 is an illustration of a third pre-charge circuit architecture with multiple pre-charge cells and multiple write assist cells, according to some embodiments of the present disclosure. FIGS. 11A and 11B are illustrations of a combined pre-charge cell and write assist cell and an associated layout, respectively, according to some embodiments of the present disclosure. FIG. 12 is an illustration of a memory system with a pre-charge cell for each column of memory cells in a memory array, according to some embodiments of the present disclosure. FIG. 13 is an illustration of a memory system with multiple pre-charge cells for each column of memory cells in a memory array, according to some embodiments of the present disclosure. FIG. 14 is an illustration of example waveforms associated with the operation of a memory system with a pre-charge circuit, according to some embodiments of the present disclosure. FIG. 15 is an illustration of a method for a pre-charge operation performed on a memory system, according to some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are merely examples and are not intended to be limiting. In addition, the present disclosure repeats reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and, unless indicated otherwise, does not in itself dictate a relationship between the various embodiments and/or configurations discussed. The following disclosure describes aspects of a static random access memory (SRAM). Specifically, the disclosure describes different embodiments related to an SRAM pre-charge circuit. For ease of explanation, certain SRAM circuit elements and control circuits are disclosed to facilitate in the description of the different embodimen