US-12621976-B2 - Sram cell structure with 3 p-channel transistors and 3 n-channel transistors and method of operating the sram cell

US12621976B2US 12621976 B2US12621976 B2US 12621976B2US-12621976-B2

Abstract

Provided is an SRAM cell structure having 3 P-channel transistors and 3 N-channel transistors. The SRAM cell device includes a first inverter composed of a CMOS; a second inverter composed of a CMOS, the input terminal of which is connected to the output terminal of the first inverter, and the output terminal of which is connected to the input terminal of the first inverter; a first access transistor connected between the bit line (BL) and the input terminal of the first inverter; and a second access transistor connected in parallel with the first access transistor. The first access transistor is composed of an N-channel transistor and is switched by the WL signal. The second access transistor is composed of a P-channel transistor and is switched by the inverse signal ( WWL ) of the WRITE signal.

Inventors

Sung Min Hong

Assignees

GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY

Dates

Publication Date: 20260505
Application Date: 20240403
Priority Date: 20240131

Claims (11)

1 . An SRAM cell structure with 3 P-channel transistors and 3 N-channel transistors, the SRAM cell structure comprising; a first inverter composed of a CMOS; a second inverter composed of a CMOS, an input terminal of which is connected to an output terminal of the first inverter, and an output terminal of which is connected to an input terminal of the first inverter; a first access transistor connected between bit line (BL) and the input terminal of the first inverter; and a second access transistor connected between the bit line (BL) and the input terminal of the first inverter and connected in parallel with the first access transistor; wherein the first access transistor is composed of an N-channel transistor and the second access transistor is composed of a P-channel transistor, wherein a gate electrode of the first access transistor is connected to a word line (WL) and the first access transistor is switched by a signal of the WL, and wherein an inverse signal ( WWL ) of a WRITE signal (WWL) is input to a gate electrode of the second access transistor and the second access transistor is switched by the inverse signal WWL .
2 . The SRAM cell structure with 3 P-channel transistors and 3 N-channel transistors of claim 1 , wherein an N-channel transistor of the second inverter is composed of an element having a driving capability greater than that of the first access transistor.
3 . The SRAM cell structure with 3 P-channel transistors and 3 N-channel transistors of claim 1 , wherein an N-channel transistor of the second inverter is composed of an element having a driving capability smaller than the sum of the driving capabilities of the first and second access transistors.
4 . The SRAM cell structure with 3 P-channel transistors and 3 N-channel transistors of claim 2 , wherein the driving capability of a transistor is a maximum drain current (I D ) that can flow in the transistor.
5 . The SRAM cell structure with 3 P-channel transistors and 3 N-channel transistors of claim 1 , wherein a P-channel transistor of the second inverter is composed of an element having a driving capability smaller than the sum of the driving capabilities of the first and second access transistors.
6 . The SRAM cell structure with 3 P-channel transistors and 3 N-channel transistors of claim 3 , wherein the driving capability of a transistor is a maximum drain current (I D ) that can flow in the transistor.
7 . The SRAM cell structure with 3 P-channel transistors and 3 N-channel transistors of claim 5 , wherein the driving capability of a transistor is a maximum drain current (I D ) that can flow in the transistor.
8 . The SRAM cell structure with 3 P-channel transistors and 3 N-channel transistors of claim 1 , wherein the SRAM cell structure is manufactured in a vertically stacked form using vertically stacked complementary field-effect transistor (CFET) technology, and transistors with the same type of channel in the SRAM cell are placed in one layer.
9 . A method of operating a SRAM cell structure comprising a first inverter composed of a CMOS, a second inverter composed of a CMOS, a first access transistor composed of an N-channel transistor and connected between a bit line (BL) and the input terminal of the first inverter, and a second access transistor composed of a P-channel transistor and connected in parallel with the first access transistor, the method comprising the following steps for a read operation: (a1) precharging the bit line (BL) with a first voltage corresponding to signal ‘1’ and setting a WRITE signal (WWL) to ‘0’; (a2) applying the voltage corresponding to the signal ‘1’ to a word line (WL) connected to a gate electrode of the first access transistor to turn on the first access transistor; (a3) applying a voltage corresponding to the inverse signal ( WWL ) of the WRITE signal (WWL=0) to a gate electrode of the second access transistor to turn off the second access transistor; (a4) sensing a second voltage of the bit line after a preset time has elapsed from the state in which the first access transistor is turned on and the second access transistor is turned off; (a5) detecting a difference between the first voltage and the second voltage of the bit line; and (a6) determining the stored data of the SRAM cell according to the detected difference of the bit line.
10 . The method of operating the SRAM cell structure according to claim 9 , further comprising the following steps for a write operation: (b1) setting the WRITE signal (WWL) to ‘1’; (b2) applying the voltage corresponding to the signal ‘1’ to the word line connected to the gate electrode of the first access transistor to turn on the first access transistor; (b3) applying the voltage corresponding to the inverse signal ( WWL ) of the WRITE signal (WWL=1) to the gate electrode of the second access transistor to turn on the second access transistor; and (b4) applying a voltage corresponding to a signal intended to be stored in the SRAM cell to the bit line and turning off the first and second access transistors after a preset time has elapsed.
11 . The method of operating the SRAM cell structure according to claim 9 , wherein in the step (a6), if the detected difference of the bit line is greater than a preset reference value, determining the stored data of the SRAM cell to be ‘0’, otherwise, determining the stored data of the SRAM cell to be ‘1’.

Description

TECHNICAL FIELD The present invention relates to an SRAM cell structure and a method of operating the SRAM cell. More specifically, the SRAM cell structure according to the present invention consists of three P-transistors and three N-transistors, allowing the application of vertically stacked CFET technology. As a result, according to the present invention, not only can an SRAM cell be manufactured in a smaller area of the silicon, but also the read and write operations can be easily implemented. BACKGROUND ART To date, research on scaling of logic semiconductor devices has continued. Recently, attempts have been made to reduce the area of silicon used per a transistor by applying methods reducing the area of standard cells instead of method reducing the line width of channel. However, as these methods also reach their limits, technology for vertically stacked complementary field-effect transistors (hereinafter referred to as ‘CFET’) has recently been developed. CFET technology is a technology that designs N-type transistors and P-type transistors by vertical stacking. Therefore, CFET technology can manufacture two transistors in the installation area of one transistor, thereby increasing the transistor density of the chip. As a result, by using CFET technology, an area reduction of ideally 50% is possible. Meanwhile, a Static Random Access Memory (hereinafter referred to as ‘SRAM’) is a memory with static characteristics that retains information while power is supplied. FIGS. 1A and 1B are circuit diagrams showing a conventional SRAM cell structure. FIG. 1A is a circuit diagram indicated with transistors, and FIG. 1B is a circuit diagram indicated with inverters. As shown in FIGS. 1A and 1B, the SRAM Cell consists of two inverters whose inputs and outputs are interconnected to each other and two access transistors connected to the input and output terminals of the inverters, respectively. The inverter is composed of CMOS composed of N-channel transistor and P-channel transistor. The access transistors are also called the pass-gate transistor and are composed of N-channel transistors. Therefore, the conventional SRAM Cell consists of a total of 6 transistors, that is, 4 N-channel transistors and 2 P-channel transistors. A word line ((WL) is connected to the gate electrodes of the access transistors, a bit line (BL) is connected to the drain electrode of one access transistor, and a bit line bar (BL) is connected to the drain electrode of the remaining access transistor. The aforementioned SRAM can operate faster and more stably than DRAM because the SRAM does not require a refresh operation. Because of these operating characteristics, the SRAM is used in a variety of applications that require high-speed data access, and is especially widely used as a cache memory within the central processing unit of a computer. However, the SRAM Cell consisting of six transistors is not only structurally more complex but also larger in size than the DRAM consisting of one transistor and a capacitor. Therefore, various efforts have been attempted to improve integration while reducing the size of SRAM. As a method to reduce the size of SRAM, Korean Patent No. 10-1579958 was proposed. The title of the aforementioned patent is “5-transistor SRAM cell”. The SRAM cell of the aforementioned patent includes two cross-coupled inverters each having two complementary transistors, and an N-channel transistor switch connected to a bit line and a word line. Meanwhile, another method of reducing the size of SRAM is to configure the SRAM cell in a two-layer stacked structure by applying the above-described CFET technology. However, since the conventional SRAM cell consists of 4 N-channel transistors and 2 P-channel transistors, the total area of the SRAM cell is determined by the area of the layer where the 4 N-channel transistors are formed. Therefore, this method has the problem of not significantly improving the overall integration. Meanwhile, Chang Liu and Sung Kyu Lim presented a paper titled “Ultra-High Density 3D SRAM Cell Designs for Monolithic 3D Integration”. In this paper, the access transistors are composed of NMOSFET and PMOSFET. As a result, the SRAM Cell consists of 3 N-channel transistors and 3 P-channel transistors. FIGS. 2A and 2B are circuit diagrams showing read and write operations respectively in the 3P3N 3D SRAM Cell structure presented in the paper by Chang Liu and Sung Kyu Lim. Referring to FIGS. 2A and 2B, in this structure, the gate overdrive voltage of the NMOSFET (M5), which is an access transistor, is lowered when the voltage of Q is slightly greater than 0 Volt. Accordingly, Q cannot be charged. Therefore, it is difficult to write VDD to Q. Also, when writing VDD to Q, Q should be 0 Volt. However, PMOSFET (M6), which is an access transistor, also loses its discharge ability when Q becomes even slightly smaller than VDD. Therefore, the SRAM Cell with the above-described structure has difficulty in the write