US-12621977-B2 - Method of forming memory device

Abstract

According to one or more embodiments of the disclosure, a method of forming a memory device including a memory region and a periphery region is provided. The method comprises: providing a first insulating layer in the memory region and the periphery region; removing a first part of the first insulating layer in the periphery region and leaving a second part of the first insulating layer in the memory region; providing a second insulating layer on the second part of the first insulating layer in the memory region, the second insulating layer and the second part of the first insulating layer forming a layer stack in the memory region; and providing at least part of a gate stack in the periphery region, the gate stack including an overlapping part over the layer stack in the memory region, the overlapping part in a boundary region between the memory region and the periphery region.

Inventors

• Yasuyuki Sakogawa

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260505

Application Date

20231129

Claims (20)

1. 1 . A method of forming a memory device including a memory region and a periphery region, the method comprising: providing a first insulating layer in the memory region and the periphery region; removing a first part of the first insulating layer in the periphery region, a second part of the first insulating layer remaining in the memory region; providing a second insulating layer on the second part of the first insulating layer in the memory region, the second insulating layer and the second part of the first insulating layer forming a layer stack in the memory region; and providing at least part of a gate stack in the periphery region, the gate stack including an overlapping part over the layer stack in the memory region, the overlapping part in a boundary region between the memory region and the periphery region.
2. 2 . The method according to claim 1 , wherein providing the first insulating layer includes nitride deposition.
3. 3 . The method according to claim 2 , wherein the first insulating layer includes nitride.
4. 4 . The method according to claim 1 , wherein removing the first part of the first insulating layer in the periphery region includes removing the first part at the boundary region between the memory region and the periphery region.
5. 5 . The method according to claim 1 , wherein providing the second insulating layer includes performing oxidation in the memory region to oxidize an upper part of the first insulating layer in the memory region.
6. 6 . The method according to claim 5 , wherein the first insulating layer includes nitride, and the second insulating layer includes oxidized nitride.
7. 7 . The method according to claim 5 , wherein the oxidation is performed in the memory region and the periphery region.
8. 8 . The method according to claim 1 , further comprising providing a mask layer on the gate stack in the periphery region and the layer stack in the memory region, wherein the mask layer covers the periphery region and a part of an upper surface of the layer stack in the memory region, and the part of the upper surface of the layer stack in the memory region covered by the mask layer is in the boundary region.
9. 9 . The method according to claim 8 , wherein the overlapping part of the gate stack in the boundary region is formed by photo and etching processes.
10. 10 . The method according to claim 1 , further comprising providing a slanted side surface of the overlapping part in the boundary region.
11. 11 . The method according to claim 10 , providing the slanted side surface includes adjusting an etching condition including at least one of a bias voltage and a gas flow rate.
12. 12 . The method according to claim 1 , wherein providing the at least part of the gate stack in the periphery region includes providing a gate metal layer, a gate silicon layer, and a gate insulating layer on top of each other.
13. 13 . The method according to claim 1 , further comprising: removing the overlapping part; and providing a gate element in the periphery region and at least one of a bit contact and a bit line in the memory region.
14. 14 . A method of forming a memory device including a memory region and a periphery region, the method comprising: providing a first insulating layer in the memory region and the periphery region; removing a first part of the first insulating layer in the periphery region, a second part of the first insulating layer remaining in the memory region; providing a second insulating layer on the second part of the first insulating layer in the memory region, the second insulating layer and the second part of the first insulating layer forming a layer stack in the memory region; providing at least part of a gate stack in the periphery region; and providing an edge part of the gate stack that overlaps an edge part of the layer stack in a boundary region between the periphery region and the memory region, the overlapping edge part of the gate stack including a slanted side surface.
15. 15 . The method according to claim 14 , further comprising removing part of an upper part of the periphery region to provide a step structure at the boundary region, wherein providing the at least part of the gate stack includes providing the at least part of the gate stack on the step structure, and providing the overlapping edge part includes providing the overlapping edge part on the step structure.
16. 16 . The method according to claim 14 , wherein providing the overlapping edge part includes providing a mask layer to cover the boundary region.
17. 17 . A method of forming a memory device including a memory region and a periphery region, the method comprising: depositing a first insulating layer over a semiconductor substrate in the memory region and the periphery region; removing the first insulating layer in the periphery region and an upper part of the periphery region at a boundary region with the memory region, a part of the first insulating layer remaining in the memory region; performing oxidation on the remaining part of the first insulating layer in the memory region and on the upper part of the periphery region to provide an oxide layer in the memory region and the periphery region, the oxide layer in the memory region forming a layer stack with the remaining part of the first insulating layer in the memory region; and depositing a plurality of gate layers forming at least part of a gate stack, the at least part of the gate stack including, in the boundary region, an edge part that overlaps an edge part of the layer stack in the memory region.
18. 18 . The method according to claim 17 , wherein the overlapping edge part includes a slanted side surface.
19. 19 . The method according to claim 17 , wherein the at least part of the gate stack includes a gate metal layer, a gate silicon layer, and a gate insulating layer on top of each other.
20. 20 . The method according to claim 17 , wherein the remaining part of the first insulating layer in the memory region includes nitride, and the oxide layer in the memory region includes oxidized nitride.

Description

CROSS REFERENCE TO RELATED APPLICATION(S) This application claims priority to U.S. Provisional Application No. 63/484,272, filed Feb. 10, 2023. The aforementioned application is incorporated herein by reference, in its entirety, for any purpose. BACKGROUND A memory device may include memory regions and periphery regions. The memory regions include memory banks of memory cells that are accessed for data read and write. The periphery regions are provided adjacent to the memory regions and include various circuits for memory operations. Certain multiple processes are performed to form memory regions and peripheral regions on a semiconductor substrate or a semiconductor wafer. During the processes, a particular care is taken to a boundary between adjacent memory and periphery regions. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts a block diagram of a memory device including a memory region and a periphery region in a plan view according to an embodiment of the disclosure. FIG. 2 depicts a process of forming at least part of a memory device including a memory region and a periphery region in a cross-sectional view according to an embodiment of the disclosure. FIG. 3 depicts a process of forming at least part of a memory device including a memory region and a periphery region in a cross-sectional view according to an embodiment of the disclosure. FIG. 4 depicts a process of forming at least part of a memory device including a memory region and a periphery region in a cross-sectional view according to an embodiment of the disclosure. FIG. 5 depicts a process of forming at least part of a memory device including a memory region and a periphery region in a cross-sectional view according to an embodiment of the disclosure. FIG. 6 depicts a process of forming at least part of a memory device including a memory region and a periphery region in a cross-sectional view according to an embodiment of the disclosure. FIG. 7 depicts a process of forming at least part of a memory device including a memory region and a periphery region in a cross-sectional view according to an embodiment of the disclosure. FIG. 8 depicts a process of forming at least part of a memory device including a memory region and a periphery region in a cross-sectional view according to an embodiment of the disclosure. FIG. 9 depicts a process of forming at least part of a memory device including a memory region and a periphery region in a cross-sectional view according to an embodiment of the disclosure. FIG. 10 depicts a process of forming at least part of a memory device including a memory region and a periphery region in a cross-sectional view according to an embodiment of the disclosure. FIG. 11 depicts a process of forming at least part of a memory device including a memory region and a periphery region in a cross-sectional view according to an embodiment of the disclosure. DETAILED DESCRIPTION Various example embodiments of the disclosure will be described below in detail with reference to the accompanying drawings. The following detailed descriptions refer to the accompanying drawings that show, by way of illustration, specific aspects in which embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure. Other embodiments may be utilized, and structure, logical and electrical changes may be made without departing from the scope of the disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments. In the descriptions, common or related elements and elements that are substantially the same are denoted with the same signs, and the descriptions thereof may be reduced or omitted. In the drawings, the dimensions and dimensional ratios of each unit do not necessarily match the actual dimensions and dimensional ratios in the embodiments. FIG. 1 depicts an example of a block diagram of a memory device 100 in a plan view according to an embodiment of the disclosure. The memory device 100 may be one example of a semiconductor device. The memory device 100 may be one example of an apparatus. The memory device 100 includes one or more memory regions (may also be referred to as cell regions) 110 and one or more periphery regions (may also be referred as peripheral regions) 111. The memory regions 110 include a plurality of memory banks of memory cells. In the example, the memory device 100 includes a pair of the memory regions 110 arranged in two rows that are extending in one direction (for example, X-direction in the drawing) and neighboring with each other in another direction (for example, Y-direction perpendicular to X-direction in the drawing). The memory regions 110 of the pair include, respectively, a first group of memory banks BANK0-BANK7 (B0-B7) and a second group of memory banks BANK8-BANK15 (B8-B15). T