US-12621979-B2 - Multi-tier memory structure with graded characteristics

US12621979B2US 12621979 B2US12621979 B2US 12621979B2US-12621979-B2

Abstract

Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.

Inventors

Abhishek Anil Sharma
Vishak Venkatraman
Eva Vo
Yue Zhong
Yu-Che Chiu
Moshe Dolejsi
Lorenzo Ferrari
Akash Kannegulla
Deepyanti Taneja
Mark Armstrong
Kamal H. Baloch
Travis W. LaJoie
Afrin Sultana
Albert B. Chen
Vamsi Evani
Yang Yang
Juan G. Alzate-Vinasco
Fatih Hamzaoglu
Forough Mahmoudabadi
Shailesh Kumar Madisetti
Van H. Le
Timothy JEN
Cheng Tan
Jisoo Kim
Miriam R. Reshotko

Assignees

INTEL CORPORATION

Dates

Publication Date: 20260505
Application Date: 20220512

Claims (20)

1 . An integrated circuit, comprising: a device layer including a plurality of semiconductor devices; an interconnect structure above the device layer and including a plurality of interconnect layers; and a multi-tier memory structure within the interconnect structure, the memory structure including a first tier and a second tier above the first tier, the first tier including first memory cells and the second tier including second memory cells, the first memory cells including first transistors and first capacitors, and the second memory cells including second transistors and second capacitors, wherein at least one transistor characteristic or capacitor characteristic of the first memory cells is graded with respect to at least one transistor characteristic or capacitor characteristic of the second memory cells.
2 . The integrated circuit of claim 1 , wherein the memory structure includes an uppermost tier and a lowermost tier and one or more additional tiers between the uppermost and lowermost tiers, and at least one transistor characteristic or capacitor characteristic is incrementally graded from a maximum value associated with one of the uppermost or lowermost tiers to a minimum value associated with the other one of the uppermost or lowermost tiers.
3 . The integrated circuit of claim 1 , wherein the at least one transistor characteristic or capacitor characteristic is with respect to a concentration of oxygen or sulfur vacancies within the first and second transistors, the second transistors having a higher concentration of oxygen or sulfur vacancies relative to the first transistors.
4 . The integrated circuit of claim 1 , wherein the at least one transistor characteristic or capacitor characteristic is with respect to a concentration of an elemental semiconductor material within a channel layer of the first and second transistors, the second transistors having a lower concentration of the elemental semiconductor material relative to the first transistors.
5 . The integrated circuit of claim 1 , wherein the at least one transistor characteristic or capacitor characteristic is with respect to a concentration of an elemental semiconductor material within a channel layer of the first and second transistors, the second transistors having a higher concentration of the elemental semiconductor material relative to the first transistors.
6 . The integrated circuit of claim 1 , wherein the at least one transistor characteristic or capacitor characteristic is with respect to area of a contact-to-channel interface within the first and second transistors, the second transistors having a larger area of contact-to-channel interface relative to the first transistors.
7 . The integrated circuit of claim 1 , wherein the at least one transistor characteristic or capacitor characteristic is with respect to channel area between the source and drain contacts within the first and second transistors, the second transistors having a larger channel area between the source and drain contacts relative to the first transistors.
8 . A printed circuit board comprising the integrated circuit of claim 1 .
9 . An integrated circuit, comprising: a plurality of semiconductor devices; an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers; a first thin film transistor (TFT) structure within a first interconnect layer of the plurality of stacked interconnect layers; a first metal-insulator-metal (MIM) capacitor coupled to a first contact of the first TFT structure; a second TFT structure within a second interconnect layer of the plurality of stacked interconnect layers, the second interconnect layer being over the first interconnect layer; and a second metal-insulator-metal (MIM) capacitor coupled to a second contact of the second TFT structure; wherein the first MIM capacitor has a larger capacitance compared to the second MIM capacitor.
10 . The integrated circuit of claim 9 , wherein the first MIM capacitor comprises first metal electrodes and the second MIM capacitor comprises second metal electrodes, wherein an area between the first metal electrodes is greater than an area between the second metal electrodes.
11 . The integrated circuit of claim 9 , wherein the first MIM capacitor comprises a first dielectric layer between first metal electrodes and the second MIM capacitor comprises a second dielectric layer between second metal electrodes, wherein the first dielectric layer is thinner than the second dielectric layer.
12 . The integrated circuit of claim 9 , wherein the first TFT structure is one TFT structure of a first array of TFT structures within the first interconnect layer, and the second TFT structure is one TFT structure of a second array of TFT structures within the second interconnect layer.
13 . An integrated circuit, comprising: a plurality of semiconductor devices; an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers; a first thin film transistor (TFT) structure within a first interconnect layer of the plurality of stacked interconnect layers, the first TFT structure comprising a first semiconductor region on a first gate dielectric; and a second TFT structure within a second interconnect layer of the plurality of stacked interconnect layers, the second interconnect layer being over the first interconnect layer, the second TFT structure comprising a second semiconductor region on a second gate dielectric; wherein the first semiconductor region has at least one of a lower concentration of oxygen vacancies, a higher concentration of gallium, a lower concertation of indium, a higher concentration of nitrogen, a lower width, or a lower thickness compared to the second semiconductor region.
14 . The integrated circuit of claim 13 , wherein the first and second semiconductor regions each comprise oxygen, indium, gallium, and zinc.
15 . The integrated circuit of claim 13 , wherein nitrogen within each of the first and second semiconductor regions has a highest concentration along a top surface of each of the first and second semiconductor regions.
16 . The integrated circuit of claim 13 , wherein the first gate dielectric is thicker than the second gate dielectric.
17 . The integrated circuit of claim 13 , wherein the first semiconductor region has a higher concentration of any of nitrogen, helium, or carbon compared to the second semiconductor region.
18 . The integrated circuit of claim 13 , wherein the second semiconductor region has a higher concentration of any of hydrogen, fluorine, or chlorine compared to the first semiconductor region.
19 . The integrated circuit of claim 13 , wherein the first TFT structure comprises a first contact coupled to a first metal-insulator-metal (MIM) capacitor and wherein the second TFT structure comprises a second contact coupled to a second metal-insulator-metal (MIM) capacitor.
20 . The integrated circuit of claim 19 , wherein the first MIM capacitor has a larger capacitance compared to the second MIM capacitor.

Description

FIELD OF THE DISCLOSURE The present disclosure relates to integrated circuits, and more particularly, to multi-tier memory structures in interconnect layers. BACKGROUND As integrated circuits continue to scale downward in size, a number of challenges arise. For instance, as transistor area decreases, so too do the dimensions for interconnects made to the various transistor structures, such as gate structures, drain regions, and source regions. Structures formed in such interconnect layers may be more susceptible to parasitic effects as they become more densely packed, or more susceptible to process effects as more and more layers are fabricated over them. Accordingly, there remain a number of non-trivial challenges with respect to the formation of backend structures in integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a cross-sectional view that illustrates an example portion of an integrated circuit configured with an interconnect region having tiers of memory structures over a plurality of semiconductor devices, in accordance with an embodiment of the present disclosure. FIG. 1B is a plan view of an array of memory structures and generally illustrates structures formed across different interconnect layers, in accordance with an embodiment of the present disclosure. FIGS. 2A-2J are cross-sectional views that collectively illustrate an example process for forming a thin film transistor (TFT) memory structure, in accordance with an embodiment of the present disclosure. FIG. 3 illustrates a cross-section view of a chip package containing one or more semiconductor dies, in accordance with some embodiments of the present disclosure. FIG. 4 illustrates a computing system including one or more integrated circuits, as variously described herein, in accordance with an embodiment of the present disclosure. Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of this disclosure. As will be further appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For instance, while some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and/or rounded corners), and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used. DETAILED DESCRIPTION Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure generally includes memory cells, with each memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. In such cases, the TFT structure allows the capacitor to be accessed during write operations (to store a memory bit) and read operations (to read a previously-stored bit). Although the techniques can be used in any number of integrated circuit applications, they are particularly useful with respect to interconnect regions over size-constrained transistors of a given device layer. The transistors of the device layer can be, for example, finFETs, gate-all-around transistors, or other transistor technologies, and may be used for any number of functions, such as logic operations, storage operations, high-frequency operations, and input/output (I/O) operations, to name a few examples. An interconnect structure or region above or below a given device layer may include any number of interconnect layers. Some such interconnect layers may just contain interconnect features, while other such interconnect layers may just contain memory structures (e.g., TFTs and/or capacitors) or a combination of memory structures and interconnect features. According to some embodiments, the memory structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Due to process effects from forming a given array of memory structures affecting all previously-formed arrays on lower tiers, various characteristics of the memory arrays can be altered as more tiers are fabricated. Certain geometric and/or material parameters of the memory structures can be intentionally altered in a graded fashion across any number of tiers to compensate for the process effects which affect any lower tiers. The grading can be done in a relatively linear or interpolative manner, moving from the lowermost tier to the uppermost tier (or vice-versa, depending on the process building direction)