US-12621980-B2 - Semiconductor device having gate structure and method for manufacturing the same

Abstract

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a first bit-line extending in a first direction and a first word-line extending in a second direction substantially perpendicular to the first direction. The semiconductor device also includes a first channel. The first bit-line and the first word-line are electrically coupled to the first channel. The semiconductor device also includes a first gate line disposed between the first bit-line and the first word-line. The first gate line is electrically coupled to the first channel and configured to close the first channel once the first bit-line and the first word-line are shorted together through the first channel.

Inventors

• Chung-Peng Hao

Assignees

• NANYA TECHNOLOGY CORPORATION

Dates

Publication Date

20260505

Application Date

20230915

Claims (9)

1. 1 . A semiconductor device, comprising: a first bit-line extending in a first direction; a first word-line extending in a second direction substantially perpendicular to the first direction; a first channel, wherein the first bit-line and the first word-line are electrically coupled to the first channel; a first gate line disposed between the first bit-line and the first word-line, wherein the first gate line is electrically coupled to the first channel and configured to close the first channel once the first bit-line and the first word-line are shorted together through the first channel; wherein the first channel penetrates the first gate line and the first word-line; wherein the first channel terminates at the first word-line; a second bit-line extending in the first direction; a second channel, wherein the first word-line and the second bit-line are electrically coupled to the second channel, wherein the first gate line is configured to close the first channel without closing the second channel; a second word-line extending in the second direction; and a third channel, wherein the second word-line and the first bit-line are electrically coupled to the third channel.
2. 2 . The semiconductor device of claim 1 , wherein the first channel and the second channel are aligned.
3. 3 . The semiconductor device of claim 1 , wherein the first channel and the third channel are not aligned.
4. 4 . The semiconductor device of claim 1 , further comprising: a second gate line disposed between the first bit-line and the second word-line, wherein the second gate line is electrically coupled to the third channel and configured to close the third channel once the first bit-line and the second word-line are shorted together through the third channel.
5. 5 . The semiconductor device of claim 1 , further comprising: a landing pad disposed between the first channel and the first bit-line.
6. 6 . The semiconductor device of claim 5 , wherein the landing pad defines a concave corner.
7. 7 . The semiconductor device of claim 6 , wherein the first channel terminates at the first word-line.
8. 8 . The semiconductor device of claim 1 , wherein the first channel penetrates a gate stack comprising the first gate line and the first word-line.
9. 9 . The semiconductor device of claim 1 , wherein an aspect ratio of the first channel is greater than about 13.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a divisional application of U.S. Non-Provisional application Ser. No. 17/940,365 filed Sep. 8, 2022, which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure relates to a semiconductor device having a gate line and a method for manufacturing the same, and more particularly, to a gate line electrically coupled to a channel of an access transistor. DISCUSSION OF THE BACKGROUND A memory array includes memory cells, each of which has a storage capacitor and an access transistor. The drain of the access transistor may be connected to a bit-line and the source of the access transistor may be connected to a node of the storage capacitor. The gate (which is also known as a word-line) of the access transistor may function as a switch to control a channel of the access transistor between the source and the drain. The channel may be formed by, for example, defining a hole through layers using photolithography and etching and then filling the hole with appropriate materials. As memory cell density increases and critical dimensions decreases the aspect ratio of such channels continues to increase. This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed herein constitutes prior art with respect to the present disclosure, and no part of this Discussion of the Background may be used as an admission that any part of this application constitutes prior art with respect to the present disclosure. SUMMARY One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a first bit-line extending in a first direction and a first word-line extending in a second direction substantially perpendicular to the first direction. The semiconductor device also includes a first channel. The first bit-line and the first word-line are electrically coupled to the first channel. The semiconductor device also includes a first gate line disposed between the first bit-line and the first word-line. The first gate line is electrically coupled to the first channel and configured to close the first channel once the first bit-line and the first word-line are shorted together through the first channel. Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a first bit-line extending in a first direction and a first gate line extending in a second direction substantially perpendicular to the first direction. The semiconductor device also includes a second gate line extending in the second direction. The semiconductor device also includes a first channel disposed between the first gate line and the second gate line. The first gate line is electrically coupled to the first channel and configured to close the first channel once the first bit-line and the first word-line are shorted together through the first channel. Another aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate and forming a first gate stack on the substrate. The first gate stack includes a first word-line and a first gate line over the first word-line. The method also includes forming a first channel in the first gate stack and forming a bit-line over the first gate line. By using a gate line disposed between a word-line and a bit-line, a control voltage may be supplied to one or more access transistors for closing channel(s) of the one or more access transistors once a short-circuit occurs between the bit-line and the word-line through the channel(s). Therefore, the functions of the other channels connected by the bit-line may not be affected. More channels may be activated by a single bit-line. The effective read/write performance of the semiconductor device can be increased by allowing more data to be written to/read from the semiconductor device during a single operation. The foregoing has outlined rather broadly the features and technical advantages of the present disclosure so that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS A more complete understanding of the present disclosure may be derived by referring to the detailed description an