US-12621981-B2 - Semiconductor memory device

US12621981B2US 12621981 B2US12621981 B2US 12621981B2US-12621981-B2

Abstract

A semiconductor memory device includes a substrate, a bit line on the substrate, word lines provided on the bit line and spaced apart in a first direction parallel to a top surface of the substrate, a back gate electrode provide between a pair of adjacent word lines among the word lines, active patterns provided between the back gate electrode and the pair of adjacent word lines, contact patterns respectively provided on the active patterns, a first back gate insulating pattern provided between the bit line and the back gate electrode, and a second back gate insulating pattern and a third back gate insulating pattern which are provided on the back gate electrode, where the back gate upper insulating pattern includes a material having a first dielectric constant and the back gate lower insulating pattern includes a material having a second dielectric constant that is greater than the first dielectric constant.

Inventors

Euichul JEONG
Sang-Woon Lee
Sangho Lee
Moonyoung JEONG

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20230918
Priority Date: 20221017

Claims (20)

1 . A semiconductor memory device comprising: a bit line extending in a first direction; a first word line extending in a second direction intersecting the first direction on the bit line; a second word line extending in the second direction and spaced apart from the first word line in the first direction; a back gate electrode extending in the second direction between the first word line and the second word line; first active patterns provided between the first word line and the back gate electrode, the first active patterns being spaced apart in the second direction; second active patterns provided between the second word line and the back gate electrode, the second active patterns being spaced apart in the second direction; contact patterns connected to the first active patterns and the second active patterns; a back gate lower insulating pattern provided between the back gate electrode and the bit line; and a back gate upper insulating pattern provided on the back gate electrode, wherein the back gate upper insulating pattern comprises a material having a first dielectric constant and the back gate lower insulating pattern comprises a material having a second dielectric constant that is greater than the first dielectric constant.
2 . The semiconductor memory device of claim 1 , wherein the first dielectric constant is between about 1 to about 4.
3 . The semiconductor memory device of claim 1 , wherein the back gate lower insulating pattern and the back gate upper insulating pattern are vertically spaced apart, and wherein the back gate electrode between the back gate lower insulating pattern and the back gate upper insulating pattern.
4 . The semiconductor memory device of claim 1 , wherein the contact patterns comprise first contact patterns connected to the first active patterns and second contact patterns connected to the second active patterns, wherein at least a portion of the first contact patterns is spaced apart from at least a portion of the second contact patterns, and wherein the back gate upper insulating pattern is provided between the portion of the first contact patterns and the portion of the second contact patterns.
5 . The semiconductor memory device of claim 1 , wherein the back gate upper insulating pattern contacts a top surface of the back gate electrode, and wherein the back gate upper insulating pattern extends in a third direction that is perpendicular to the first direction and the second direction.
6 . The semiconductor memory device of claim 1 , wherein the first active patterns and the second active patterns are formed of a single-crystalline semiconductor material.
7 . The semiconductor memory device of claim 1 , wherein the back gate upper insulating pattern comprises at least one of silicon oxide, SiOC, and air.
8 . A semiconductor memory device comprising: a substrate; a bit line on the substrate; word lines provided on the bit line and spaced apart in a first direction parallel to a top surface of the substrate; a back gate electrode provide between a pair of adjacent word lines among the word lines; active patterns provided between the back gate electrode and the pair of adjacent word lines; contact patterns respectively provided on the active patterns; a first back gate insulating pattern provided between the bit line and the back gate electrode; and a second back gate insulating pattern and a third back gate insulating pattern which are provided on the back gate electrode, wherein the second back gate insulating pattern comprises a material having a first dielectric constant and the third back gate insulating pattern comprises a material having a second dielectric constant that is greater than the first dielectric constant.
9 . The semiconductor memory device of claim 8 , wherein the second back gate insulating pattern is provided between the back gate electrode and the third back gate insulating pattern.
10 . The semiconductor memory device of claim 9 , wherein the second back gate insulating pattern contacts a top surface of the back gate electrode, and wherein the third back gate insulating pattern contacts a top surface of the second back gate insulating pattern.
11 . The semiconductor memory device of claim 8 , wherein a first portion of the third back gate insulating pattern is provided between the back gate electrode and the second back gate insulating pattern, and wherein the second back gate insulating pattern is provided between the first portion of the third back gate insulating pattern and a remaining portion of the third back gate insulating pattern.
12 . The semiconductor memory device of claim 11 , wherein the third back gate insulating pattern contacts a top surface of the back gate electrode, and wherein the third back gate insulating pattern extends along a top surface and a bottom surface of the second back gate insulating pattern.
13 . The semiconductor memory device of claim 8 , wherein the third back gate insulating pattern at least partially surrounds the second back gate insulating pattern, and wherein the third back gate insulating pattern contacts a top surface of the back gate electrode.
14 . The semiconductor memory device of claim 8 , wherein the first dielectric constant is between about 1 to about 4.
15 . The semiconductor memory device of claim 8 , wherein the second back gate insulating pattern is provided between the contact patterns in the first direction.
16 . The semiconductor memory device of claim 8 , wherein the second back gate insulating pattern comprises at least one of silicon oxide, SiOC, and air.
17 . The semiconductor memory device of claim 8 , wherein the first back gate insulating pattern, the second back gate insulating pattern and the third back gate insulating pattern extend in a second direction that is parallel to the top surface of the substrate and that is perpendicular to the first direction.
18 . A semiconductor memory device comprising: a substrate; a bit line extending in a first direction on the substrate; a first active pattern; a second active pattern spaced apart from the first active pattern in the first direction on the bit line; a back gate electrode provided between the first active pattern and the second active pattern, the back gate electrode extending in a second direction and intersecting the bit line; a first word line provided adjacent to the first active pattern and extending in the second direction; a second word line provided adjacent to the second active pattern and extending in the second direction; at least one first gate insulating pattern provided between the first active pattern and the first word line; at least one second gate insulating pattern provided between the second active pattern and the second word line; at least one third gate insulating pattern provided between the first active pattern and the back gate electrode, at least one fourth gate insulating pattern provided between the second active pattern and the back gate electrode; contact patterns connected to the first active pattern and the second active pattern; a back gate lower insulating pattern provided between the bit line and the back gate electrode; a back gate upper insulating pattern provided on the back gate electrode and between the contact patterns; at least one first insulating pattern provided between the first word line and the bit line, at least one second insulating pattern provided between the first word line and a corresponding contact pattern of the contact patterns; at least one third insulating pattern provided between the second word line and the bit line; at least one fourth insulating pattern provided between the second word line and a corresponding contact pattern of the contact patterns; and data storage patterns respectively connected to the contact patterns, wherein the back gate upper insulating pattern comprises a material having a first dielectric constant and the back gate lower insulating pattern comprises a material having a second dielectric constant that is greater than the first dielectric constant.
19 . The semiconductor memory device of claim 18 , wherein the first dielectric constant is between about 1 to about 4.
20 . The semiconductor memory device of claim 18 , wherein the back gate upper insulating pattern comprises at least one of silicon oxide, SiOC, and air.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority to Korean Patent Application No. 10-2022-0133171, filed on Oct. 17, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device with improved electrical characteristics and integration density. An electronic system requiring data storage may require a semiconductor device capable of storing high-capacity data. To meet performance and price objectives of a semiconductor device while increasing data storage capacity of the semiconductor device, it may be required to increase an integration density of the semiconductor device. An integration density of a two-dimensional (2D) or planar semiconductor device may be mainly determined by an area where a unit memory cell occupies, and thus the integration density of the 2D or planar semiconductor device may be greatly affected by a technique of forming fine patterns. However, since high-priced apparatuses are needed to form fine patterns, the integration density of 2D semiconductor devices is still limited. Thus, semiconductor memory devices have been developed to improve their integration density, resistance and current driving capability. Information disclosed in this Background section has already been known to or derived by the inventors before or during the process of achieving the embodiments of the present application, or is technical information acquired in the process of achieving the embodiments. Therefore, it may contain information that does not form the prior art that is already known to the public. SUMMARY One or more example embodiments provide a semiconductor memory device with improved integration density and electrical characteristics. Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments. According to an aspect of an example embodiment, a semiconductor memory device may include a bit line extending in a first direction, a first word line extending in a second direction intersecting the first direction on the bit line, a second word line extending in the second direction and spaced apart from the first word line in the first direction, a back gate electrode extending in the second direction between the first word line and the second word line, first active patterns provided between the first word line and the back gate electrode, the first active patterns being spaced apart in the second direction, second active patterns provided between the second word line and the back gate electrode, the second active patterns being spaced apart in the second direction, contact patterns respectively connected to the first active patterns and the second active patterns, a back gate lower insulating pattern provided between the back gate electrode and the bit line, and a back gate upper insulating pattern provided on the back gate electrode, where the back gate upper insulating pattern may include a material having a first dielectric constant and the back gate lower insulating pattern may include a material having a second dielectric constant that is greater than the first dielectric constant. According to an aspect of an example embodiment, a semiconductor memory device may include a substrate, a bit line on the substrate, word lines provided on the bit line and spaced apart in a first direction parallel to a top surface of the substrate, a back gate electrode provide between a pair of adjacent word lines among the word lines, active patterns provided between the back gate electrode and the pair of adjacent word lines, contact patterns respectively provided on the active patterns, a first back gate insulating pattern provided between the bit line and the back gate electrode, and a second back gate insulating pattern and a third back gate insulating pattern which are provided on the back gate electrode, where the back gate upper insulating pattern may include a material having a first dielectric constant and the back gate lower insulating pattern may include a material having a second dielectric constant that is greater than the first dielectric constant. According to an aspect of an example embodiment, a semiconductor memory device may include a substrate, a bit line extending in a first direction on the substrate, a first active pattern, a second active pattern spaced apart from the first active pattern in the first direction on the bit line, a back gate electrode provided between the first active pattern and the second active pattern, the back gate electrode extending in a second direction and intersecting the bit line, a first word line provided adjacent to the first active pattern and extending in the second direction, a second word line provid