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US-12621982-B2 - Semiconductor device with pad structure and method for fabricating the same

US12621982B2US 12621982 B2US12621982 B2US 12621982B2US-12621982-B2

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a pad structure positioned above the substrate and including a bottom portion and two side portions, wherein the bottom portion is positioned parallel to a top surface of the substrate, and the two side portions are positioned on two sides of the bottom portion and extending along a direction parallel to a normal of the top surface of the substrate; and an insulator film surrounding the pad structure. A top surface of the insulator film is at a vertical level greater than a vertical level of a top surface of the pad structure.

Inventors

  • Tsu-Chieh AI

Assignees

  • NANYA TECHNOLOGY CORPORATION

Dates

Publication Date
20260505
Application Date
20231006

Claims (8)

  1. 1 . A semiconductor device, comprising: a substrate; a pad structure positioned above the substrate and comprising a bottom portion and two side portions, wherein the bottom portion is positioned parallel to a top surface of the substrate, and the two side portions are positioned on two sides of the bottom portion and extending along a direction parallel to a normal of the top surface of the substrate; an insulator film surrounding the pad structure; a bottom contact positioned under the pad structure and contacting the bottom portion of the pad structure; and a top contact positioned on the bottom portion of the pad structure; wherein a top surface of the insulator film is at a vertical level greater than a vertical level of a top surface of the pad structure.
  2. 2 . The semiconductor device of claim 1 , wherein top surfaces of the two side portions are at a vertical level greater than a vertical level of a top surface of the bottom portion.
  3. 3 . The semiconductor device of claim 1 , wherein the top surfaces of the two side portions have a rounding cross-sectional profile.
  4. 4 . The semiconductor device of claim 1 , wherein a width of the top contact is less than a width of the pad structure.
  5. 5 . The semiconductor device of claim 1 , wherein a width of the top contact is greater than a width of the bottom portion.
  6. 6 . The semiconductor device of claim 1 , wherein a width of the bottom contact is less than a width of the bottom portion, wherein a width of the top contact is greater than the width of the bottom contact.
  7. 7 . The semiconductor device of claim 1 , further comprising a drain positioned in the substrate and electrically coupled to the pad structure through the bottom contact.
  8. 8 . The semiconductor device of claim 1 , further comprising a capacitor structure positioned above the pad structure and electrically coupled to the pad structure through the top contacts.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation application of U.S. Non-Provisional application Ser. No. 17/484,988 filed Sep. 24, 2021, which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly, to a semiconductor device with a pad structure and a method for fabricating the semiconductor device the pad structure. DISCUSSION OF THE BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic equipment. The dimensions of semiconductor devices are continuously being scaled down to meet the increasing demand of computing ability. However, a variety of issues arise during the scaling-down process, and such issues are continuously increasing. Therefore, challenges remain in achieving improved quality, yield, performance, and reliability and reduced complexity. This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure. SUMMARY One aspect of the present disclosure provides a semiconductor device including a substrate; a pad structure positioned above the substrate and including a bottom portion and two side portions, wherein the bottom portion is positioned parallel to a top surface of the substrate, and the two side portions are positioned on two sides of the bottom portion and extending along a direction parallel to a normal of the top surface of the substrate; and an insulator film surrounding the pad structure. A top surface of the insulator film is at a vertical level greater than a vertical level of a top surface of the pad structure. In some embodiments, top surfaces of the two side portions are at a vertical level greater than a vertical level of a top surface of the bottom portion. In some embodiments, the top surfaces of the two side portions have a rounding cross-sectional profile. In some embodiments, the semiconductor device includes a bottom contact positioned under the pad structure and contacting the pad structure. In some embodiments, the semiconductor device includes a top contact positioned on the pad structure. In some embodiments, a width of the top contact is less than a width of the pad structure. In some embodiments, a width of the top contact is greater than a width of the bottom portion. In some embodiments, a width of the top contact is less than a width of the bottom portion. In some embodiments, the semiconductor device includes a drain positioned in the substrate and electrically coupled to the pad structure through the bottom contact. In some embodiments, the semiconductor device includes a capacitor structure positioned above the pad structure and electrically coupled to the pad structure through the top contacts. Another aspect of the present disclosure provides a method for fabricating a semiconductor device including providing a substrate including a top surface; forming a dielectric layer on the substrate; forming an insulator film on the dielectric layer; patterning the insulator film to form a pad opening along the insulator film and expose a portion of the dielectric layer; conformally forming a layer of first conductive material on a top surface of the insulator film and in the pad opening; forming an under layer to completely fill the pad opening; and removing the layer of first conductive material formed on the top surface of the insulator film to form a pad structure. The pad structure includes a bottom portion and two side portions, the bottom portion is formed parallel to the top surface of the substrate, and the two side portions are formed on two sides of the bottom portion and extending along a direction parallel to a normal of the top surface of the substrate. In some embodiments, the under layer includes a photoresist material. In some embodiments, an isotropic etch process is performed to remove the layer of first conductive material formed on the top surface of the insulator film. In some embodiments, the method for fabricating the semiconductor device includes forming a bottom contact in the dielectric layer. The bottom contact is electrically connected to the pad structure. In some embodiments, the method for fabricating the semiconductor device includes forming a top contact on the bottom portion of the pad structure. In some embodiments, the method for fabricating the semiconductor device includes forming a top contact on the bottom portion and the two side portion