US-12621983-B2 - Semiconductor device including vertical channel region

Abstract

A semiconductor device includes a substrate, a first gate structure and a second gate structure on the substrate, a single back gate structure between the first gate structure and the second gate structure, a first structure including a first vertical channel region extending in a vertical direction, at least a portion of the first vertical channel region between the first gate structure and the single back gate structure, and a second structure including a second vertical channel region extending in the vertical direction. The second structure is spaced apart from the first structure, and at least a portion of the second vertical channel region is between the second gate structure and the single back gate structure.

Inventors

• Moonyoung JEONG
• Kiseok LEE
• Sangho Lee
• Hyungjun NOH

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20230321

Priority Date

20220330

Claims (20)

1. 1 . A semiconductor device comprising: a substrate; a first gate structure and a second gate structure on the substrate, the first gate structure and the second gate structure spaced apart from each other in a first direction; a single back gate structure between the first gate structure and the second gate structure, wherein the single back gate structure includes a back gate dielectric layer and a back gate electrode, and wherein the back gate electrode of the single back gate structure is spaced apart from the first gate structure and the second gate structure; a first structure including a first vertical channel region extending in a vertical direction, wherein at least a portion of the first vertical channel region is between the first gate structure and the single back gate structure; and a second structure including a second vertical channel region extending in the vertical direction, the second structure spaced apart from the first structure, wherein at least a portion of the second vertical channel region is between the second gate structure and the single back gate structure, wherein the first gate structure includes a first gate electrode and a first gate dielectric layer, the first gate dielectric layer between the first gate electrode and the first structure, wherein the second gate structure includes a second gate electrode and a second gate dielectric layer, the second gate dielectric layer between the second gate electrode and the second structure, and wherein the back gate dielectric layer includes a first back gate dielectric portion between the back gate electrode and the first structure, and a second back gate dielectric portion between the back gate electrode and the second structure.
2. 2 . The semiconductor device of claim 1 , wherein the first structure further includes a first source/drain below the first vertical channel region and a second source/drain above the first vertical channel region, and the second structure further includes a third source/drain below the second vertical channel region and a fourth source/drain above the second vertical channel region.
3. 3 . The semiconductor device of claim 1 , wherein the first vertical channel region includes a first side surface and a second side surface opposing each other in the first direction, and a third side surface and a fourth side surface opposing each other in a second direction, the second direction intersecting the first direction, the second vertical channel region includes a fifth side surface and a sixth side surface opposing each other in the first direction, and a seventh side surface and an eighth side surface opposing each other in the second direction, the first gate structure covers at least a portion of each of the third and fourth side surfaces and the first side surface, the second gate structure covers at least a portion of each of the seventh and eighth side surfaces and the fifth side surface, and the single back gate structure covers the second side surface and the sixth side surface.
4. 4 . The semiconductor device of claim 3 , wherein the first gate structure has a first width in a portion covering the first side surface, and the single back gate structure has a second width in a portion covering the second side surface, the second width different than the first width.
5. 5 . The semiconductor device of claim 3 , wherein the first gate structure covers a first portion of each of the third and fourth side surfaces, the second gate structure covers a second portion of each of the seventh and eighth side surfaces, and the single back gate structure covers a third portion of each of the third and fourth side surfaces and a fourth portion of each of the seventh and eighth side surfaces.
6. 6 . The semiconductor device of claim 5 , wherein in each of the third and fourth side surfaces, the first portion is greater than the third portion, and in each of the seventh and eighth side surfaces, the second portion is greater than the fourth portion.
7. 7 . The semiconductor device of claim 1 , wherein the first gate electrode has a first vertical thickness, and the back gate electrode has a second vertical thickness, the second vertical thickness different than the first vertical thickness.
8. 8 . The semiconductor device of claim 1 , wherein the first structure includes a first horizontal portion and a first vertical portion extending from a portion of the first horizontal portion in the vertical direction, and the first vertical portion includes the first vertical channel region, the second structure includes a second horizontal portion and a second vertical portion extending from a portion of the second horizontal portion in the vertical direction, and the second vertical portion includes the second vertical channel region, at least a portion of the first gate structure is on the first horizontal portion, and at least a portion of the second gate structure is on the second horizontal portion.
9. 9 . The semiconductor device of claim 8 , further comprising: a first contact plug on the first vertical portion; a second contact plug on the first horizontal portion; a data storage structure on the first contact plug; and a bit line on the second contact plug, wherein the first gate structure includes a region between the second contact plug and the first vertical portion, and at least a portion of the bit line is on a level higher than a level of the first vertical portion.
10. 10 . The semiconductor device of claim 8 , further comprising: a contact plug on the first vertical portion; a data storage structure on the contact plug; and a bit line below the first horizontal portion.
11. 11 . A semiconductor device comprising: a substrate; a first structure on the substrate, the first structure including a first horizontal portion and a pair of first vertical portions extending from the first horizontal portion in a vertical direction, wherein the pair of first vertical portions are spaced apart from each other; a second structure on the substrate, the second structure including a second horizontal portion and a pair of second vertical portions extending from the second horizontal portion in the vertical direction, wherein the pair of second vertical portions are spaced apart from each other; a pair of first gate structures on the first horizontal portion between the pair of first vertical portions, the pair of first gate structures extending in a horizontal direction; a pair of second gate structures on the second horizontal portion, between the pair of second vertical portions, the pair of second gate structures extending in the horizontal direction; and a single back gate structure between the first structure and the second structure.
12. 12 . The semiconductor device of claim 11 , wherein a first gate structure of the pair of first gate structures is in contact with a first vertical portion of the pair of first vertical portions, the first vertical portion includes a first vertical channel region, the first vertical channel region includes a first side surface and a second side surface opposing each other, and a third side surface and a fourth side surface opposing each other, the first gate structure covers at least a portion of each of the third and fourth side surfaces and the first side surface, and the single back gate structure covers at least the second side surface.
13. 13 . The semiconductor device of claim 12 , wherein in the first vertical channel region, a corner between the first side surface and the third side surface is round, and a corner between the first side surface and the fourth side surface is round.
14. 14 . The semiconductor device of claim 11 , further comprising: an isolation region defining a first active region and a second active region on the substrate, wherein the first structure is on the first active region, and the second structure is on the second active region.
15. 15 . The semiconductor device of claim 11 , further comprising: multiple contact structures on the pair of first vertical portions; a contact plug on the first horizontal portion, the contact plug electrically connected to the first horizontal portion; a data storage structure on the contact structures, the data storage structure electrically connected to the contact structures; and a bit line on the contact plug, the bit line electrically connected to the contact plug, wherein the contact plug is between the pair of first gate structures.
16. 16 . A semiconductor device comprising: a first memory cell array; a second memory cell array spaced apart from the first memory cell array; and a back gate control circuit on at least one side of each of the first and second memory cell arrays, each of the first and second memory cell arrays includes transistors, word lines, bit lines, data storage structures, and back gate lines, the back gate lines intersect the first and second memory cell arrays, and the back gate lines are electrically connected to the back gate control circuit, the bit lines extend in a first direction, the word lines and the back gate lines are parallel to each other and spaced apart from each other, and the word lines and the back gate lines extend in a second direction perpendicular to the first direction, the transistors include a first pair of transistors sharing a single first lower source/drain, and a second pair of transistors sharing a single second lower source/drain, a single first back gate line of the back gate lines is between the first pair of transistors and the second pair of transistors, and each of the first pair of transistors further includes a vertical channel region on the single first lower source/drain and an upper source/drain on the vertical channel region.
17. 17 . The semiconductor device of claim 16 , wherein the word lines comprise gate electrodes of the first pair of transistors, and a first gate electrode of the gate electrodes covers at least three side surfaces of the vertical channel region.
18. 18 . The semiconductor device of claim 17 , wherein the single first back gate line covers at least three side surfaces of the vertical channel region, and the vertical channel region is between the single first back gate line and the first gate electrode.
19. 19 . The semiconductor device of claim 16 , wherein the back gate control circuit is configured to simultaneously control a plurality of the back gate lines.
20. 20 . The semiconductor device of claim 1 , wherein the first gate electrode includes: a first electrode portion facing the first vertical channel region in the first direction; and a second electrode portion not facing the first vertical channel region in the first direction, wherein a distance between the first electrode portion and the back gate electrode in the first direction is greater than a distance between the second electrode portion and the back gate electrode in the first direction.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims benefit of priority to Korean Patent Application No. 10-2022-0039883 filed on Mar. 30, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. FIELD Some example embodiments relate to a semiconductor device including a vertical channel region and/or a method of fabricating the same. BACKGROUND Research is being conducted into reducing the size of elements constituting semiconductor devices and to improve performance thereof. For example, in dynamic random-access memory (DRAM) devices, research is being conducted to reliably and stably form elements having a reduced size. However, as sizes of the elements are reduced, it becomes increasingly difficult to implement transistors having a desired degree of performance. SUMMARY Some example embodiments provide a semiconductor device having improved performance. According to an example embodiment, a semiconductor device includes a substrate, a first gate structure and a second gate structure on the substrate, the first gate structure and the second gate structure spaced apart from each other, a single back gate structure between the first gate structure and the second gate structure, the single back gate structure spaced apart from the first gate structure and the second gate structure, a first structure including a first vertical channel region extending in a vertical direction, wherein at least a portion of the first vertical channel region is between the first gate structure and the single back gate structure, and a second structure including a second vertical channel region extending in the vertical direction, the second structure spaced apart from the first structure, wherein at least a portion of the second vertical channel region is between the second gate structure and the single back gate structure. According to an example embodiment, a semiconductor device includes a substrate, a first structure on the substrate, the first structure including a first horizontal portion and a pair of first vertical portions extending from the first horizontal portion in a vertical direction, wherein the pair of first vertical portions are spaced apart from each other, a second structure on the substrate, the second structure including a second horizontal portion and a pair of second vertical portions extending from the second horizontal portion in the vertical direction, wherein the pair of second vertical portions are spaced apart from each other, a pair of first gate structures on the first horizontal portion between the pair of first vertical portions, the pair of first gate structures extending in a horizontal direction, a pair of second gate structures on the second horizontal portion, between the pair of second vertical portions, the pair of second gate structures extending in the horizontal direction, and a single back gate structure between the first structure and the second structure. According to an example embodiment, a semiconductor device including a first memory cell array, a second memory cell array spaced apart from the first memory cell array, and a back gate control circuit on at least one side of each of the first and second memory cell arrays, wherein each of the first and second memory cell arrays includes transistors, word lines, bit lines, data storage structures, and back gate lines, the back gate lines intersect the first and second memory cell arrays, and the back gate lines are electrically connected to the back gate control circuit, the bit lines extend in a first direction, the word lines and the back gate lines are parallel to each other and spaced apart from each other, and the word lines and the back gate lines extend in a second direction perpendicular to the first direction, the transistors include a first pair of transistors sharing a single first lower source/drain, and a second pair of transistors sharing a single second lower source/drain, a single first back gate line of the back gate lines is between the first pair of transistors and the second pair of transistors, and each of the first pair of transistors further includes a vertical channel region on the single first lower source/drain and an upper source/drain on the vertical channel region. BRIEF DESCRIPTION OF DRAWINGS The above and other aspects, features, and advantages of the inventive concepts will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings. FIGS. 1, 2A, and 2B are conceptual views of a semiconductor device according to an example embodiment. FIG. 3A is a conceptual plan view illustrating a modified example of a semiconductor device according to an example embodiment. FIG. 3B is a conceptual plan view illustrating a modified example of a semiconductor device according to an example embodiment. FIG. 3C is a conceptual plan view illustrating a modified example of a semic