US-12621984-B2 - Semiconductor structure and fabrication method therefor

US12621984B2US 12621984 B2US12621984 B2US 12621984B2US-12621984-B2

Abstract

This invention relates to a semiconductor structure and a fabrication method therefor. The method for fabricating a semiconductor structure includes: providing a substrate, where a shallow trench isolation structure is formed on the substrate; forming a plurality of transistor accommodating grooves in the active regions, where there is a spacing between the transistor accommodating groove and the shallow trench isolation structure; forming a columnar structure in the transistor accommodating groove, where the columnar structure includes a source, a conductive channel, and a drain that are sequentially disposed in a direction away from the substrate; etching the active region located within the spacing and the active region located between adjacent columnar structures in the same active region to form a bit line trench, where the bit line trench surrounds the source; and forming a bit line that surrounds and connects the source in the bit line trench.

Inventors

Shuai Guo

Assignees

CHANGXIN MEMORY TECHNOLOGIES, INC.

Dates

Publication Date: 20260505
Application Date: 20230509
Priority Date: 20210907

Claims (14)

1 . A method for fabricating a semiconductor structure, comprising: providing a substrate, wherein a plurality of shallow trench isolation structures are formed in the substrate, and configured to isolate a plurality of active regions arranged at intervals in the substrate; forming a plurality of transistor accommodating grooves in an active region, wherein there is a spacing between an transistor accommodating groove and a shallow trench isolation structure; forming a columnar structure in the transistor accommodating groove, wherein the columnar structure comprises a source, a conductive channel, and a drain that are sequentially disposed in a direction away from the substrate; forming a contact plug on the drain; etching the active region located within the spacing and located between adjacent columnar structures to form a bit line trench, wherein the bit line trench surrounds the source; forming a bit line that surrounds and contacts a sidewall of the source in the bit line trench, wherein the bit line is located within the spacing and located between adjacent columnar structures and the sidewall of the source is perpendicular to the substrate; forming a first dielectric material layer that covers the bit line, the conductive channel, the drain, and the contact plug; forming a gate-all-around word line that corresponds and surrounds the conductive channel on a surface of the first dielectric material layer facing away from the conductive channel, wherein there is an air gap between adjacent gate-all-around word lines; forming a second dielectric material layer that covers the gate-all-around word line on a surface of the first dielectric material layer facing away from the contact plug; and etching the second dielectric material layer and the first dielectric material layer to obtain a first dielectric layer and a second dielectric layer, wherein the contact plug is exposed from the first dielectric layer and the second dielectric layer.
2 . The method for fabricating a semiconductor structure according to claim 1 , wherein the forming a columnar structure in the transistor accommodating groove comprises: filling a semiconductor material in the transistor accommodating groove to form the source; depositing the semiconductor material on the substrate to form a semiconductor film that covers the source; and patterning the semiconductor film to form the drain and the conductive channel, wherein each of an orthographic projection of the drain on the substrate and an orthographic projection of the conductive channel on the substrate overlaps an orthographic projection of the source on the substrate.
3 . The method for fabricating a semiconductor structure according to claim 1 , wherein the etching the active region located within the spacing and located between adjacent columnar structures to form a bit line trench comprises: forming a first sacrificial layer that covers an exposed surface of the columnar structure and an exposed surface of the substrate; patterning the first sacrificial layer and etching the active region located within the spacing and located between adjacent columnar structures based on a pattern of the first sacrificial layer; and removing the first sacrificial layer.
4 . The method for fabricating a semiconductor structure according to claim 1 , wherein the forming a gate-all-around word line that corresponds and surrounds the conductive channel on a surface of the first dielectric material layer facing away from the conductive channel comprises: depositing a metal material on the first dielectric material layer; etching the metal material until an upper surface of the metal material is flush with an upper surface of the columnar structure, or an upper surface of the metal material is lower than an upper surface of the columnar structure, to obtain a metal pattern layer; forming a second sacrificial layer that covers an exposed surface of the first dielectric material layer and the metal pattern layer; patterning the second sacrificial layer and etching the metal pattern layer based on a pattern of the second sacrificial layer to obtain the gate-all-around word line that corresponds and surrounds the conductive channel; and removing the second sacrificial layer.
5 . The method for fabricating a semiconductor structure according to claim 4 , wherein the metal material comprises tungsten metal.
6 . The method for fabricating a semiconductor structure according to claim 1 , wherein before the etching the second dielectric material layer and the first dielectric material layer, the method further comprises: forming a third dielectric material layer on the second dielectric material layer; and forming a plurality of contact windows in the third dielectric material layer to obtain a third dielectric layer; the etching the second dielectric material layer and the first dielectric material layer to obtain the first dielectric layer and the second dielectric layer, wherein the contact plug is exposed from the first dielectric layer and the second dielectric layer comprises: etching the second dielectric material layer and the first dielectric material layer based on the contact windows to obtain the first dielectric layer and the second dielectric layer, wherein the contact plug is exposed from the first dielectric layer and the second dielectric layer; and after the etching the second dielectric material layer and the first dielectric material layer to obtain the first dielectric layer and the second dielectric layer, wherein the contact plug is exposed from the first dielectric layer and the second dielectric layer, the method further comprises: forming a contact pad in contact with the contact plug in the contact window.
7 . The method for fabricating a semiconductor structure according to claim 6 , wherein the forming a contact pad in contact with the contact plug in the contact window comprises: forming a pad material layer in the contact window and on a surface of the third dielectric layer; and removing the pad material layer on the surface of the third dielectric layer by using a chemical mechanical polishing process, wherein the pad material layer remaining in the contact window is the contact pad.
8 . The method for fabricating a semiconductor structure according to claim 1 , wherein a material of the bit line and/or the contact plug comprises bismuth metal.
9 . The method for fabricating a semiconductor structure according to claim 1 , wherein a material of the columnar structure comprises molybdenum disulfide.
10 . The method for fabricating a semiconductor structure according to claim 3 , wherein the forming the bit line that surrounds and contacts the sidewall of the source in the bit line trench comprises: forming a bit line material layer that fills the bit line trench and covers an exposed surface of the first sacrificial layer; patterning the bit line material layer to form the bit line that surrounds and contacts the sidewall of the source in the bit line trench.
11 . A semiconductor structure, comprising: a substrate, wherein a plurality of shallow trench isolation structures are formed in the substrate, and configured to isolate a plurality of active regions arranged at intervals in the substrate; a transistor accommodating groove, wherein the transistor accommodating groove is located in the active region, and there is a spacing between the transistor accommodating groove and the shallow trench isolation structure; a columnar structure, wherein the columnar structure is located in the transistor accommodating groove and comprises a source, a conductive channel, and a drain that are sequentially disposed in a direction away from the substrate; a bit line, wherein the bit line is located within the spacing and located between adjacent columnar structures, and the bit line surrounds and contacts a sidewall of the source that is perpendicular to the substrate; a contact plug, wherein the contact plug is located on a surface of the drain facing away from the conductive channel; a first dielectric layer, wherein the first dielectric layer covers the bit line and is located on a sidewall of the conductive channel, the drain, and the contact plug; a gate-all-around word line, wherein the gate-all-around word line is located on a surface of the first dielectric layer facing away from the conductive channel and surrounds the conductive channel; and a second dielectric layer, wherein the second dielectric layer is located on a surface of the first dielectric layer facing away from the contact plug and covers the gate-all-around word line, wherein there is an air gap between adjacent gate-all-around word lines.
12 . The semiconductor structure according to claim 11 , wherein a material of the columnar structure comprises molybdenum disulfide; and/or a material of the bit line comprises bismuth metal.
13 . The semiconductor structure according to claim 11 , wherein the semiconductor structure further comprises: a third dielectric layer, wherein the third dielectric layer has a contact window and covers at least the second dielectric layer; and a contact pad, wherein the contact pad is located in the contact window and is in contact with the contact plug.
14 . The semiconductor structure according to claim 11 , wherein a material of the contact plug comprises bismuth metal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation application of International Patent Application No. PCT/CN2022/071594, filed on Jan. 12, 2022, which claims priority to Chinese Patent Application No. 202111044659.3, filed with the China National Intellectual Property Administration on Sep. 7, 2021, and entitled “SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREFOR.” The above-referenced applications are incorporated herein by reference in their entirety. TECHNICAL FIELD This invention relates to the field of semiconductor integrated circuit manufacturing technologies, and in particular, to a semiconductor structure and a fabrication method therefor. BACKGROUND Dynamic random access memory (DRAM) is a semiconductor memory commonly used in electronic devices such as computers. It is composed of a plurality of storage units, each of which includes a storage capacitor and a transistor electrically connected to the storage capacitor. The transistor includes a gate, a source region, and a drain region. The gate of the transistor is configured to electrically connect to a word line. The source region of the transistor is configured to form a bit line contact region for electrical connection to a bit line through a bit line contact structure. The drain region of the transistor is configured to form a storage node contact region for electrical connection to the storage capacitor through a storage node contact structure. While using a vertical gate-all-around transistor (VGAA transistor) can effectively reduce the feature size of the DRAM, it can also lead to an excessively large contact resistance between the metal material and the semiconductor material due to the Schottky barrier and the metal-induced gap states (MIGS) when the channel width is continuously reduced. Consequently, the output current of the transistor might not meet the operation requirements of the DRAM, thereby adversely affecting the electrical performance of the DRAM. SUMMARY Some example embodiments of this invention provide a semiconductor structure and a fabrication method therefor. Some embodiments of this invention provide a method for fabricating a semiconductor structure, including the following steps: providing a substrate, where a shallow trench isolation structure is formed on the substrate, and configured to isolate a plurality of active regions arranged at intervals in the substrate; forming a plurality of transistor accommodating grooves in the active regions, where there is a spacing between the transistor accommodating groove and the shallow trench isolation structure; forming a columnar structure in the transistor accommodating groove, where the columnar structure includes a source, a conductive channel, and a drain that are sequentially disposed in a direction away from the substrate; etching the active region located within the spacing and the active region located between adjacent columnar structures in the same active region to form a bit line trench, where the bit line trench surrounds the source; and forming a bit line that surrounds and connects the source in the bit line trench. In some embodiments, the forming a columnar structure in the transistor accommodating groove includes the following steps: filling a semiconductor material in the transistor accommodating groove to form the source; depositing the semiconductor material on the substrate to form a semiconductor film that covers the source; and patterning the semiconductor film to form the drain and the conductive channel, where each of an orthographic projection of the drain on the substrate and an orthographic projection of the conductive channel on the substrate overlaps an orthographic projection of the source on the substrate. In some embodiments, the etching the active region located within the spacing and the active region located between adjacent columnar structures in the same active region to form a bit line trench includes the following steps: forming a first sacrificial layer that covers an exposed surface of the columnar structure and an exposed surface of the substrate; patterning the first sacrificial layer and etching the active region located within the spacing and the active region located between adjacent columnar structures in the same active region based on a pattern of the first sacrificial layer; and removing the first sacrificial layer. In some embodiments, before forming the bit line trench, the method for fabricating a semiconductor structure further includes forming a contact plug on the drain; and correspondingly, after the forming a bit line that surrounds and connects the source in the bit line trench, the method for fabricating a semiconductor structure further includes the following steps: forming a first dielectric material layer that covers the bit line, the conductive channel, the drain, and the contact plug; forming a gate-all-around word line that corresponds and surrounds the conductive channel on a s