US-12621986-B2 - Memory device with peripheral circuitry which extends under a back end memory array

US12621986B2US 12621986 B2US12621986 B2US 12621986B2US-12621986-B2

Abstract

Techniques and mechanisms for accessing memory arrays which are formed in a back end of line (BEOL) of an integrated circuit (IC) die. In an embodiment, a differential sense amplifier of the IC die is coupled to a first array and a second array via a first bit line and a second bit line, respectively. The first bit line and the second bit line extend from a first level of BEOL memory arrays, toward a front end of line (FEOL) of the IC die, on opposite respective sides of first array, wherein the differential sense amplifier is in a footprint region for the first memory array. In another embodiment, a word line driver circuit comprises a two stage charger-discharger circuit which mitigates hot carrier injection.

Inventors

Pulkit JAIN
Juan ALZATE VINASCO
Liqiong Wei
Ozdemir Akin
Fatih Hamzaoglu

Assignees

INTEL CORPORATION

Dates

Publication Date: 20260505
Application Date: 20220607

Claims (13)

1 . An integrated circuit (IC) die comprising: a first memory array comprising first dynamic random access memory (DRAM) cells, wherein the first memory array extends in a first area of a first horizontal plane, wherein the first area comprises a maximum horizontal range of any memory cells of the first memory array which are in the first horizontal plane, and wherein a first edge of the first area is opposite a second edge of the first area; a second memory array comprising second DRAM cells, wherein the second memory array extends in a second area of the first horizontal plane, wherein the second area comprises a maximum horizontal range of any memory cells of the second memory array which are in the first horizontal plane, wherein a back end of line (BEOL) of the IC die comprises a first array level, and wherein the first memory array and the second memory array are each in the first array level; and a differential sense amplifier coupled to the first memory array and the second memory array via a first bit line and a second bit line, respectively, wherein the differential sense amplifier is to: receive a first signal and a second signal via the first bit line and the second bit line, respectively; generate, based on each of the first signal and the second signal, an output which indicates a bit value at one of the first DRAM cells or one of the second DRAM cells; wherein: the first bit line and the second bit line extend from the first array level toward a front end of line (FEOL) of the IC die; a portion of the first bit line extends vertically through the first horizontal plane at a first location which is external to the first area; the second edge is between the first location and each of the first edge and the second area; a portion of the second bit line extends vertically through the first horizontal plane at a second location which is between the first edge and the second area; and a maximum horizontal range of the differential sense amplifier in a second horizontal plane of the FEOL is within a third area of the second horizontal plane, wherein the third area is within a footprint of the first area.
2 . The IC die of claim 1 , further comprising: a third memory array comprising third DRAM cells, wherein the BEOL of the IC die comprises a second array level, and wherein the third memory array is in the second array level; and first level selection circuitry coupled between the differential sense amplifier and each of the first bit line and a third bit line, wherein the first level selection circuitry is coupled to the third memory array via the third bit line, and wherein the first level selection circuitry is to selectively couple the differential sense amplifier to either of the first array level or the second array level.
3 . The IC die of claim 2 , wherein the first level selection circuitry is in the footprint of the first area.
4 . The IC die of claim 2 , further comprising: a fourth memory array comprising fourth DRAM cells, wherein the fourth memory array is in the second array level; and second level selection circuitry coupled between the differential sense amplifier and each of the first bit line and a fourth bit line, wherein the second level selection circuitry is coupled to the fourth memory array via the fourth bit line, and wherein the second level selection circuitry is to selectively couple the differential sense amplifier to either of the first array level or the second array level.
5 . The IC die of claim 4 , wherein the first level selection circuitry and the second level selection circuitry are each in the footprint of the first area.
6 . The IC die of claim 4 , further comprising: a first word line driver circuit coupled to the second memory array via a first word line; and a second word line driver circuit coupled to the fourth memory array via a second word line; wherein the first word line driver circuit and the second word line driver circuit are each in a second footprint region corresponding to the second memory array.
7 . The IC die of claim 6 , wherein, in the second footprint region, a portion of the first word line extends vertically from the first array level toward the FEOL; and wherein a portion of the second word line extends vertically past the first array level, and toward the FEOL, in a region which is outside of a periphery of the second memory array.
8 . The IC die of claim 6 , wherein first peripheral circuitry of the IC die is to access the first memory array, the second memory array, the third memory array and the fourth memory array; wherein the first peripheral circuitry is arranged in a first tile area of the FEOL; and wherein the first tile area forms recess structures each at a respective one of opposite ends of the first tile area.
9 . The IC die of claim 8 , wherein the first peripheral circuitry comprises: the differential sense amplifier; the first level selection circuitry; the second level selection circuitry; the first word line driver circuit; the second word line driver circuit; and a third word line driver circuit coupled to a fifth memory array via a third word line, wherein a third array level of the BEOL comprises the fifth memory array.
10 . A system comprising: an integrated circuit (IC) die comprising: a first memory array comprising first dynamic random access memory (DRAM) cells, wherein the first memory array extends in a first area of a first horizontal plane, wherein the first area comprises a maximum horizontal range of any memory cells of the first memory array which are in the first horizontal plane, and wherein a first edge of the first area is opposite a second edge of the first area; a second memory array comprising second DRAM cells, wherein the second memory array extends in a second area of the first horizontal plane, wherein the second area comprises a maximum horizontal range of any memory cells of the second memory array which are in the first horizontal plane, wherein a back end of line (BEOL) of the IC die comprises a first array level, and wherein the first memory array and the second memory array are each in the first array level; and a differential sense amplifier coupled to the first memory array and the second memory array via a first bit line and a second bit line, respectively, wherein the differential sense amplifier is to: receive a first signal via the first bit line, and receive a second signal via the second bit line; and generate, based on each of the first signal and the second signal, an output which indicates a bit value at one of the first DRAM cells or one of the second DRAM cells; wherein: the first bit line and the second bit line extend from the first array level toward a front end of line (FEOL) of the IC die; a portion of the first bit line extends vertically through the first horizontal plane at a first location which is external to the first area; the second edge is between the first location and each of the first edge and the second area; a portion of the second bit line extends vertically through the first horizontal plane at a second location which is between the first edge and the second area; and a maximum horizontal range of the differential sense amplifier in a second horizontal plane of the FEOL, is within a third area of the second horizontal plane, wherein the third area is within a footprint of the first area; and a display device coupled to the IC die, the display device to display an image based on the bit value.
11 . The system of claim 10 , further comprising: a third memory array comprising third DRAM cells, wherein the BEOL of the IC die comprises a second array level, and wherein the third memory array is in the second array level; and first level selection circuitry coupled between the differential sense amplifier and each of the first bit line and a third bit line, wherein the first level selection circuitry is coupled to the third memory array via the third bit line, and wherein the first level selection circuitry is to selectively couple the differential sense amplifier to either of the first array level or the second array level.
12 . The system of claim 11 , further comprising: a fourth memory array; a first word line driver circuit coupled to the second memory array via a first word line; and a second word line driver circuit coupled to the fourth memory array via a second word line; wherein the first word line driver circuit and the second word line driver circuit are each in a second footprint region corresponding to the second memory array.
13 . The system of claim 12 , wherein, in the second footprint region, a portion of the first word line extends vertically from the first array level toward the FEOL; and wherein a portion of the second word line extends vertically past the first array level, and toward the FEOL, in a region which is outside of a periphery of the second memory array.

Description

BACKGROUND 1. Technical Field This disclosure generally relates to memory devices and more particularly, but not exclusively, to peripheral circuitry which is to provide access to a back end memory array. 2. Background Art Various types of embedded memory are monolithically integrated with a host IC (i.e., both memory and the host IC fabricated on the same chip). For embedded memory applications, reducing the overall memory array footprint helps achieve larger memories and/or reduce device cost. One form of embedded memory is embedded dynamic random access memory (eDRAM). The architecture of eDRAM is typically based on a 1T-1C cell that includes a cell “write” or “select” transistor and a storage capacitor. The back end of line (BEOL) of an integrated circuit fabrication process is the portion of IC fabrication where individual semiconductor devices (whether embedded memory or logic transistors) are interconnected to one another with electrically conductive features such as metal interconnect traces (lines) within a given metallization level and metal-filled conductive vias between multiple metallization levels. For some memory devices, a transistor of a memory cell is fabricated in the back-end-of-line (BEOL), with the channel material being a thin film semiconductor material rather than the monocrystalline semiconductor (e.g., Si) typical of front end of line (FEOL) transistors. For some eDRAM, the capacitor is also fabricated in the BEOL and electrically coupled to the transistor through one or more metal interconnect layers formed in the BEOL. Typically, memory cells implemented in a BEOL are interconnected to peripheral circuitry (e.g., address decoders) which is implemented with CMOS logic fabricated in the FEOL. The interconnection however becomes much more difficult if more than one level of memory cells is implemented in the BEOL. For example, where an IC chip includes two or more memory cell levels, the set of data lines (e.g., 1,024 bit lines) associated with each memory cell array level would need to be routed down to periphery circuitry. However, routing this many lines down from two, three, or more memory array levels would require significant area. As successive generations of embedded memory technologies continue to increase in number, variety, and capability, there is expected to be an increasing premium placed on improvements to the space efficiency of these circuit architectures. BRIEF DESCRIPTION OF THE DRAWINGS The various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which: FIG. 1 shows a cross-sectional side view diagram illustrating features of an integrated circuit (IC) structure to provide access to multiple back end memory arrays according to an embodiment. FIG. 2 shows a perspective view diagram illustrating features of an IC device to operate multiple memory arrays of a back end according to an embodiment. FIG. 3 shows a perspective view diagram illustrating features of an IC device to variously access back end memory arrays according to an embodiment. FIG. 4 shows a perspective view diagram illustrating features of an IC device to access memory arrays in various levels of a back end of line according to an embodiment. FIG. 5 shows a cross-sectional top view diagram illustrating features of an IC die to operate multiple memory arrays of a back end according to an embodiment. FIG. 6 shows a cross-sectional top view diagram illustrating features of an IC die to variously access back end memory arrays according to an embodiment. FIG. 7 shows a cross-sectional top view diagram illustrating features of an IC die to access memory arrays in various levels of a back end of line according to an embodiment. FIG. 8 shows a circuit diagram illustrating features of a word line driver 800 to facilitate communication via a word line according to an embodiment. FIG. 9 shows a timing diagram illustrating operations performed with a word line driver according to an embodiment. FIG. 10 shows a functional block diagram illustrating features of a computing device to provide access to back end memory arrays according to an embodiment. DETAILED DESCRIPTION Embodiments discussed herein variously provide techniques and mechanisms for accessing memory arrays which are formed in a back end of line of an integrated circuit (IC) die. The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any kind of mobile device and/or stationary device, such as cameras, cell phones, computer terminals, desktop computers, electronic readers, facsimile machines, kiosks, laptop computers, netbook computers, notebook computers, internet devices, payment terminals, personal digital assistants, media players and/or recorders, servers (e.g., blade server, rack mount server, combinations the