US-12621987-B2 - Memory devices and methods for forming the same

Abstract

A memory device includes a memory cell and a peripheral circuit. The memory cell includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The peripheral circuit is coupled to the bit line. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The bit line is disposed between the vertical transistor and the peripheral circuit along the first direction.

Inventors

• Wei Liu
• Hongbin Zhu
• Wenyu HUA

Assignees

• YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260505

Application Date

20230602

Priority Date

20230530

Claims (20)

1. 1 . A memory device, comprising: a memory cell comprising: a vertical transistor having a first terminal and a second terminal; a storage unit having a first end coupled to the first terminal of the vertical transistor; and a bit line coupled to the second terminal of the vertical transistor; and a peripheral circuit coupled to the bit line, wherein the vertical transistor comprises a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body; and the bit line is disposed between the vertical transistor and the peripheral circuit along the first direction.
2. 2 . The memory device of claim 1 , wherein the bit line is coupled to the second terminal of the vertical transistor via a contact and extends in a second direction perpendicular to the first direction.
3. 3 . The memory device of claim 2 , wherein the gate structure is coupled to two sides of the semiconductor body along the second direction.
4. 4 . The memory device of claim 2 , wherein the gate structure is in contact with one or more sides of the semiconductor body.
5. 5 . The memory device of claim 1 , further comprising: a bonding interface disposed between the memory cell and the peripheral circuit, wherein the bit line is coupled to the peripheral circuit through a metallic bonding pad of the bonding interface.
6. 6 . The memory device of claim 5 , further comprising: a redistribution layer disposed between the bit line and the bonding interface, wherein a second end of the storage unit is coupled to the redistribution layer through a contact structure; the bit line is coupled to the redistribution layer; and the redistribution layer is coupled to the bonding interface.
7. 7 . A memory system, comprising: a memory device configured to store data, and comprising: a memory cell comprising: a vertical transistor having a first terminal and a second terminal; a storage unit having a first end coupled to the first terminal of the vertical transistor; and a bit line coupled to the second terminal of the vertical transistor; and a peripheral circuit coupled to the bit line, wherein the vertical transistor comprises a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body; and the bit line is disposed between the vertical transistor and the peripheral circuit along the first direction; and a memory controller coupled to the memory device and configured to control the memory cell through the peripheral circuit.
8. 8 . A method for forming a memory device, comprising: forming a vertical transistor having a first terminal and a second terminal on a first substrate; forming a bit line on the second terminal; forming a bonding interface on the vertical transistor; forming a peripheral circuit on a second substrate; bonding the peripheral circuit with the bonding interface in a face-to-face manner; removing the first substrate to expose the vertical transistor; and forming a storage unit on the first terminal.
9. 9 . The method of claim 8 , wherein forming the vertical transistor having the first terminal and the second terminal on the first substrate, comprising: forming a first trench in the first substrate along a first direction and extending along a second direction perpendicular to the first direction; forming a first trench isolation in the first trench; forming a second trench in the first substrate along the first direction and extending along a third direction perpendicular to the first direction and the second direction; and forming a gate structure in the second trench.
10. 10 . The method of claim 9 , wherein after forming the second trench, a semiconductor body is formed extending along the first direction between the second trench and the first trench isolation.
11. 11 . The method of claim 10 , further comprising: forming a third trench along the first direction and extending along the third direction to divide the semiconductor body; and forming a second trench isolation in the third trench.
12. 12 . The method of claim 10 , further comprising: performing a doping operation on a first end of the semiconductor body to form the second terminal.
13. 13 . The method of claim 8 , wherein removing the first substrate to expose the vertical transistor, comprises: performing a planarization operation having the second substrate as a support substrate.
14. 14 . The method of claim 13 , further comprising, comprises: performing an implantation operation and a thermal diffusion operation on an exposed semiconductor body to form the first terminal at a second end of the semiconductor body.
15. 15 . The method of claim 8 , wherein the storage unit is formed after bonding the peripheral circuit with the bonding interface.
16. 16 . A method for forming a memory device, comprising: forming a vertical transistor on a first substrate; forming a peripheral circuit on a second substrate; bonding the peripheral circuit with the vertical transistor in a face-to-face manner; removing the first substrate to expose the vertical transistor; and forming a storage unit on the vertical transistor.
17. 17 . The method of claim 16 , wherein forming the vertical transistor on the first substrate, comprises: forming a semiconductor body on the first substrate extending along a first direction; forming a gate structure at a side of the semiconductor body; forming a second terminal at a first end of the semiconductor body; and after removing the first substrate to expose the vertical transistor, forming a first terminal at a second end of the semiconductor body.
18. 18 . The method of claim 17 , wherein bonding the peripheral circuit with the vertical transistor in the face-to-face manner, comprises: forming a bonding interface on the vertical transistor; and bonding the peripheral circuit to the bonding interface.
19. 19 . The method of claim 17 , wherein bonding the peripheral circuit with the vertical transistor in the face-to-face manner, comprises: forming a bit line on the second terminal; forming a redistribution layer on the bit line; forming a bonding interface on the redistribution layer; and bonding the peripheral circuit to the bonding interface.
20. 20 . The method of claim 16 , wherein removing the first substrate to expose the vertical transistor, comprises: removing the first substrate using the second substrate as a support substrate to expose the vertical transistor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priorities to U.S. Provisional Application No. 63/348,363, filed on Jun. 2, 2022, and C.N. Application No. 202310646869.2, filed May 30, 2023, both of which are hereby incorporated by reference in their entireties. BACKGROUND The present disclosure relates to memory devices and fabrication methods thereof. Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuits for facilitating operations of the memory array. SUMMARY In one aspect, a memory device is disclosed. The memory device includes a memory cell and a peripheral circuit. The memory cell includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The peripheral circuit is coupled to the bit line. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The bit line is disposed between the vertical transistor and the peripheral circuit along the first direction. In some implementations, the bit line is coupled to the second terminal of the vertical transistor via a contact and extends in a second direction perpendicular to the first direction. In some implementations, the gate structure is coupled to two sides of the semiconductor body along the second direction. In some implementations, the gate structure is in contact with one or more sides of the semiconductor body. In some implementations, the memory device further includes a bonding interface disposed between the memory cell and the peripheral circuit. The bit line is coupled to the peripheral circuit through a metallic bonding pad of the bonding interface. In some implementations, the memory device further includes a redistribution layer disposed between the bit line and the bonding interface. A second end of the storage unit is coupled to the redistribution layer through a contact structure, the bit line is coupled to the redistribution layer, and the redistribution layer is coupled to the bonding interface. In another aspect, a memory system is disclosed. The memory system includes a memory device configured to store data, and a memory controller coupled to the memory device. The memory device includes a memory cell and a peripheral circuit. The memory cell includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The peripheral circuit is coupled to the bit line. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The bit line is disposed between the vertical transistor and the peripheral circuit along the first direction. The memory controller is configured to control the memory cell through the peripheral circuit. In still another aspect, a method for forming a memory device is disclosed. A vertical transistor having a first terminal and a second terminal is formed on a first substrate. A bit line is formed on the second terminal. A bonding interface is formed on the vertical transistor. A peripheral circuit is formed on a second substrate. The peripheral circuit is bonded with the bonding interface in a face-to-face manner. The first substrate is removed to expose the vertical transistor. A storage unit is formed on the first terminal. In some implementations, a first trench is formed in the first substrate along a first direction and extending along a second direction perpendicular to the first direction. A first trench isolation is formed in the first trench. A second trench is formed in the first substrate along the first direction and extends along a third direction perpendicular to the first direction and the second direction. A gate structure is formed in the second trench. In some implementations, after forming the second trench, a semiconductor body is formed extending along the first direction between the second trench and the first trench isolation. In some implementations, a third trench is formed along the first direction and extends along the third direction to divide the semiconductor body, and a second trench isolation is formed in the third t