US-12621988-B2 - Semiconductor device and method of manufacturing the semiconductor device

Abstract

A semiconductor device includes: a source structure comprising a cell area and an edge area; a stack located on the edge area of the source structure; a gate structure located on the cell area of the source structure; a channel structure connected to the cell area of the source structure by extending through the gate structure; and a read-only memory area.

Inventors

• Jae Ho Kim

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260505

Application Date

20230320

Priority Date

20221007

Claims (19)

1. 1 . A semiconductor device comprising: a source structure comprising a cell area and an edge area, wherein the source structure includes a conductive material; a stack located on the edge area of the source structure and vertically overlapping the conductive material of the source structure; a gate structure located on the cell area of the source structure; a channel structure connected to the cell area of the source structure by extending through the gate structure; and a read-only memory comprising a first contact plug passing through the edge area of the source structure and a second contact plug connected to the first contact plug by extending through the stack.
2. 2 . The semiconductor device of claim 1 , wherein the read-only memory comprises a transistor electrically connected to the first contact plug.
3. 3 . The semiconductor device of claim 2 , wherein the transistor is configured to store data.
4. 4 . The semiconductor device of claim 1 , wherein the read-only memory is located in an edge area of a semiconductor chip.
5. 5 . The semiconductor device of claim 1 , wherein the stack comprises a first stack adjacent to the edge area of the source structure and a second stack spaced apart from the edge area of the source structure.
6. 6 . The semiconductor device of claim 5 , wherein a first height of the first stack is lower than a second height of the second stack.
7. 7 . The semiconductor device of claim 1 , wherein the gate structure comprises a first gate structure adjacent to the cell area of the source structure and a second gate structure spaced apart from the cell area of the source structure.
8. 8 . The semiconductor device of claim 7 , further comprising: an isolation insulating layer passing through the first gate structure and connected to the cell area of the source structure.
9. 9 . The semiconductor device of claim 1 , wherein the source structure includes polysilicon.
10. 10 . The semiconductor device of claim 1 , further comprising: an insulating spacer interposed between the first contact plug and the source structure.
11. 11 . A semiconductor device comprising: a substrate comprising a cell area and a read-only memory area; a stack located over the read-only memory area of the substrate; a gate structure located over the cell area of the substrate; a conductive source structure located between the gate structure and the substrate, and extending between the stack and the read-only memory area of the substrate to vertically overlap the stack; a channel structure connected to the conductive source structure by extending through the gate structure; a read-only memory comprising a first contact plug passing through the conductive source structure and a second contact plug connected to the first contact plug by extending through the stack; and an insulating spacer interposed between the first contact plug and the conductive source structure.
12. 12 . The semiconductor device of claim 11 , wherein the read-only memory comprises a transistor electrically connected to the first contact plug.
13. 13 . The semiconductor device of claim 12 , wherein the transistor is configured to store data.
14. 14 . The semiconductor device of claim 11 , wherein the read-only memory is located in an edge area of a semiconductor chip.
15. 15 . The semiconductor device of claim 11 , wherein the stack comprises a first stack adjacent to the read-only memory area of the substrate and a second stack spaced apart from the read-only memory area of the substrate.
16. 16 . The semiconductor device of claim 15 , wherein a first height of the first stack is lower than a second height of the second stack.
17. 17 . The semiconductor device of claim 11 , wherein the gate structure comprises a first gate structure adjacent to the cell area of the substrate and a second gate structure spaced apart from the cell area of the substrate.
18. 18 . The semiconductor device of claim 17 , further comprising: an isolation insulating layer passing through the first gate structure and connected to the cell area of the source structure.
19. 19 . The semiconductor device of claim 11 , wherein the source structure includes polysilicon.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2022-0128902 filed on Oct. 7, 2022, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. BACKGROUND 1. Technical Field Embodiments of the present disclosure relate to an electronic device and a method of manufacturing the electronic device, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. 2. Related Art The degree of integration of a semiconductor device is mainly determined by an area occupied by a unit memory cell. Recently, as the improvement in the degree of integration of a semiconductor device for forming memory cells in a single layer on a substrate reaches a limit, a three-dimensional semiconductor device for stacking memory cells on a substrate has been proposed. Furthermore, in order to improve the operational reliability of such a semiconductor device, various structures and manufacturing methods have been developed. SUMMARY In an embodiment, a semiconductor device may include: a source structure comprising a cell area and an edge area; a stack located on the edge area of the source structure; a gate structure located on the cell area of the source structure; a channel structure connected to the cell area of the source structure by extending through the gate structure; and a read-only memory area comprising a first contact plug located in the edge area of the source structure and a second contact plug connected to the first contact plug by extending through the stack. In an embodiment, a method of manufacturing a semiconductor device may include: forming a source structure; forming a first contact plug passing through the source structure; forming a first stack on the source structure; forming a first sacrificial layer passing through the first stack and connected to the first contact plug; forming a second stack on the first stack; forming a second sacrificial layer passing through the second stack and connected to the first sacrificial layer; and forming the first contact plug and a second contact plug connected to the first contact plug in a read-only memory area by replacing the first sacrificial layer and the second sacrificial layer with the second contact plug. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A and FIG. 1B are diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. FIG. 2A and FIG. 2B are diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. FIG. 3A, 3B, and FIG. 3C are diagrams for describing a semiconductor device in accordance with an embodiment. FIG. 4A, 4B, 4C, 4D, 4E, and FIG. 4F are diagrams for describing a method of manufacturing a semiconductor device in accordance with an embodiment. FIG. 5A, 5B, and FIG. 5C are diagrams for describing a method of manufacturing a semiconductor device in accordance with an embodiment. FIG. 6 is a diagram for describing a method of manufacturing a semiconductor device in accordance with an embodiment. FIG. 7 is a diagram for describing a method of manufacturing a semiconductor device in accordance with an embodiment. DETAILED DESCRIPTION Various embodiments are directed to a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the same. In an embodiment of the present technology, it is possible to provide a semiconductor device having a stable structure and improved reliability. Hereafter, embodiments in accordance with the technical spirit of the present disclosure will be described with reference to the accompanying drawings. It will be understood that when an element or layer etc., is referred to as being “on,” “connected to” or “coupled to” another element or layer etc., it can be directly on, connected or coupled to the other element or layer etc., or intervening elements or layers etc., may be present. In contrast, when an element or layer etc., is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer etc., there are no intervening elements or layers etc., present. Like numerals refer to like elements throughout. FIG. 1A and FIG. 1B are diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. FIG. 1B illustrates section ‘A’ of FIG. 1A in accordance with an embodiment. Referring to FIG. 1A and FIG. 1B, the semiconductor device may include at least one plane PL, a first peripheral circuit PR1, or a pad PAD, or a combination thereof. The semiconductor device may be a semiconductor chip 100. The planes PL may be arranged in a first direction I, in a second direction II intersecting the first direction I, or in the first direction I and the second direction II. The pad PAD and the first peripheral circuit PR1 may be located around the planes PL. For example, the pad PAD and the