US-12621989-B2 - Semiconductor devices and methods of manufacturing semiconductor devices

Abstract

A method of manufacturing a semiconductor device includes forming a molded structure of stacked and alternating interlayer insulating layers and sacrificial layers on a lower structure, forming a hole through the molded structure, forming recess regions in the sacrificial layers of the molded structure, respectively, by removing a portion of the sacrificial layers, exposed through the hole, from side surfaces of the sacrificial layers, sequentially forming a preliminary blocking pattern and a charge storage pattern in each of the recess regions, sequentially forming a tunneling layer and a channel layer in the hole, forming trenches penetrating through the molded structure, such that the trenches extend in a line shape, removing the sacrificial layers exposed by the trenches, such that the preliminary blocking pattern is exposed, and oxidizing the preliminary blocking pattern, after removing the sacrificial layers, such that a blocking pattern is formed.

Inventors

• Eunyeoung CHOI
• Joonam KIM
• Hyungjoon Kim
• Donghwa LEE
• DONGSUNG CHOI

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20221004

Priority Date

20211019

Claims (19)

1. 1 . A method of manufacturing a semiconductor device, the method comprising: forming a molded structure on a lower structure, such that the molded structure includes interlayer insulating layers and sacrificial layers alternately stacked in a vertical direction perpendicular to an upper surface of the lower structure; forming a hole penetrating through the molded structure; removing portions from side surfaces of the sacrificial layers exposed through the hole, such that recess regions are formed in the sacrificial layers of the molded structure, respectively; sequentially forming a preliminary blocking pattern and a charge storage pattern in the recess regions; sequentially forming a tunneling layer and a channel layer in the hole; forming trenches penetrating through the molded structure, such that the trenches extend in a line shape; removing the sacrificial layers through the trenches, such that the preliminary blocking pattern is exposed; and oxidizing the preliminary blocking pattern, after removing the sacrificial layers, to form a blocking pattern, wherein at least one of the preliminary blocking pattern and the charge storage pattern is formed by an epitaxy process.
2. 2 . The method as claimed in claim 1 , wherein each of the charge storage pattern and the preliminary blocking pattern is formed to have a uniform thickness in a first direction in which the recess regions extend.
3. 3 . The method as claimed in claim 2 , wherein: a thickness of the preliminary blocking pattern in the first direction is within a range of 5 angstroms to 50 angstroms, and a thickness of the charge storage pattern in the first direction is within a range of 10 angstroms to 70 angstroms.
4. 4 . The method as claimed in claim 1 , wherein the charge storage pattern is formed of at least one of silicon germanium, silicon, and indium gallium arsenide.
5. 5 . The method as claimed in claim 1 , wherein the preliminary blocking pattern is formed of a semiconductor material with impurities, the impurities including at least one of carbon and oxygen.
6. 6 . The method as claimed in claim 1 , wherein: the charge storage pattern includes a plurality of first material layers spaced apart from each other in the vertical direction, and the preliminary blocking pattern includes a plurality of second material layers spaced apart from each other in the vertical direction.
7. 7 . The method as claimed in claim 6 , wherein, in the vertical direction, a thickness of each of the plurality of first material layers and a thickness of each of the plurality of second material layers are substantially the same as a thickness of each of the sacrificial layers.
8. 8 . The method as claimed in claim 1 , wherein: side surfaces of the interlayer insulating layers are in contact with the tunneling layer; and at least a portion of upper surfaces and lower surfaces of the interlayer insulating layers are in contact with the preliminary blocking pattern and the charge storage pattern.
9. 9 . The method as claimed in claim 1 , wherein: the preliminary blocking pattern is formed of a material different from a material of the sacrificial layers; and removing the sacrificial layers is controlled to stop an etching process at boundaries between the sacrificial layers and the preliminary blocking pattern.
10. 10 . The method as claimed in claim 1 , wherein, in a first direction in which the recess regions extend, a thickness of the blocking pattern is within a range of 1.5 to 2.5 times a thickness of the preliminary blocking pattern.
11. 11 . The method as claimed in claim 1 , wherein the sacrificial layers are formed of polysilicon layers including impurities, the impurities including at least one of boron, phosphorus, arsenic, carbon, and boron fluoride.
12. 12 . The method as claimed in claim 1 , wherein: forming the molded structure on the lower structure includes sequentially forming a first horizontal conductive layer and a second horizontal conductive layer on a substrate, and forming the molded structure on the second horizontal conductive layer, forming the hole includes forming the hole through the first and second horizontal conductive layers, such that the hole extends into a portion of the substrate, and the first horizontal conductive layer is formed to penetrate through the tunneling layer to be in contact with the channel layer.
13. 13 . The method as claimed in claim 12 , wherein: the sacrificial layers are formed of polysilicon including impurities, forming the recess regions includes forming a dummy recess region from a side surface of the second horizontal conductive layer and a side surface and an upper surface of the substrate exposed by the hole, and forming the preliminary blocking pattern and the charge storage pattern includes sequentially forming a dummy preliminary blocking pattern and a dummy charge storage pattern in the dummy recess region.
14. 14 . A method of manufacturing a semiconductor device, the method comprising: forming a molded structure on a lower structure, such that the molded structure includes interlayer insulating layers and sacrificial layers alternately stacked in a vertical direction perpendicular to an upper surface of the lower structure; forming a hole penetrating through the molded structure, such that the hole is in contact with the lower structure; selectively removing portions of the sacrificial layers exposed through the hole, such that recess regions are formed in the sacrificial layers of the molded structure, with respect to the interlayer insulating layers; forming a preliminary blocking pattern in the recess regions by performing an epitaxy process on the sacrificial layers; forming a charge storage pattern in the recess regions by performing an epitaxy process on the preliminary blocking pattern, forming trenches penetrating through the molded structure; removing the sacrificial layers exposed by the trenches; and forming a blocking pattern by oxidizing the preliminary blocking pattern, exposed by removing the sacrificial layers.
15. 15 . The method as claimed in claim 14 , further comprising: forming a channel layer in the hole; wherein the trenches penetrating through the molded structure extend in a line shape; wherein the sacrificial layers are removed through the trenches; and forming gate layers to cover the blocking pattern, such that the gate layers are between the interlayer insulating layers.
16. 16 . The method as claimed in claim 15 , wherein forming the gate layers includes: forming a gate dielectric layer to cover the blocking pattern and between the interlayer insulating layers; and forming a gate conductive layer to fill the gate dielectric layer.
17. 17 . The method as claimed in claim 14 , wherein: the preliminary blocking pattern and the charge storage pattern are formed of silicon; and the preliminary blocking pattern and the charge storage pattern are in contact with the interlayer insulating layers between the interlayer insulating layers.
18. 18 . A method of manufacturing a semiconductor device, the method comprising: forming a molded structure on a substrate, such that the molded structure includes interlayer insulating layers and sacrificial layers alternately stacked; forming a hole penetrating through the molded structure, such that side surfaces of the interlayer insulating layers and side surfaces of the sacrificial layers are exposed; removing portions from the side surfaces of the sacrificial layers, such that recess regions are formed in the sacrificial layers, respectively; forming a preliminary blocking pattern in the recess regions by performing an epitaxy process on the side surfaces of the sacrificial layers; forming a charge storage pattern in the recess regions by performing an epitaxy process on a side surface of the preliminary blocking pattern; sequentially forming a tunneling layer and a channel layer in the hole; forming trenches penetrating through the molded structure; removing the sacrificial layers exposed by the trenches; forming a blocking pattern by oxidizing the preliminary blocking pattern, exposed by removing the sacrificial layers; and forming gate layers to cover the blocking pattern and between the interlayer insulating layers, wherein: one side surface of the tunneling layer is in contact with the channel layer, and another side surface of the tunneling layer is in contact with the interlayer insulating layers and the charge storage pattern, and an upper surface or a lower surface of the charge storage pattern is coplanar with an upper surface or a lower surface of the blocking pattern.
19. 19 . The method as claimed in claim 18 , wherein: the charge storage pattern is formed of at least one of silicon germanium, silicon, and indium gallium arsenide; and the preliminary blocking pattern is a silicon layer including at least one of carbon and oxygen.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims benefit of priority to Korean Patent Application No. 10-2021-0139120, filed on Oct. 19, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND 1. Field The present disclosure relates to semiconductor devices and methods of manufacturing the same. 2. Description of the Related Art In a data storage system requiring data storage, there is an increasing demand for a semiconductor device which may store high-capacity data. Accordingly, research into methods of increasing data storage capacity of a semiconductor device has been conducted. For example, a semiconductor device including three-dimensionally arranged memory cells, rather than two-dimensionally arranged memory cells, has been proposed as a method of increasing data storage capacity of a semiconductor device. SUMMARY According to an example embodiment, a method of manufacturing a semiconductor device may include forming a molded structure including interlayer insulating layers and sacrificial layers alternately stacked on a lower structure in a vertical direction, perpendicular to an upper surface of the lower structure; forming a hole to penetrate through the molded structure; forming recess regions by removing a portion of the sacrificial layers, exposed through the hole, from side surfaces of the sacrificial layers; sequentially forming a preliminary blocking pattern and a charge storage pattern in the recess regions; sequentially forming a tunneling layer and a channel layer in the hole; forming trenches penetrating through the molded structure and extending in a line shape; removing the sacrificial layers exposed by the trenches; and oxidizing the preliminary blocking pattern, exposed by removing the sacrificial layer, to form a blocking pattern. According to another example embodiment, a method of manufacturing a semiconductor device may include forming a molded structure including sacrificial layers and interlayer insulating layers alternately stacked on a lower structure in a vertical direction, perpendicular to an upper surface of the lower structure; forming a hole penetrating through the molded structure to be in contact with the lower structure; forming recess regions by selectively removing a portion of the sacrificial layers, exposed from the hole, with respect to the interlayer insulating layer; forming a preliminary blocking pattern in the recess regions performing an epitaxy process from the sacrificial layers; and forming a charge storage pattern in the recess regions performing an epitaxy process from the preliminary blocking pattern. According to yet another example embodiment, a method of manufacturing a semiconductor device may include forming a molded structure including interlayer insulating layers and sacrificial layers alternately stacked on a substrate; forming a hole to penetrate through the molded structure and to expose side surfaces of the interlayer insulating layers and side surfaces of the sacrificial layers; forming recess regions extending toward the sacrificial layers by removing a portion of the exposed sacrificial layers from the side surfaces of the sacrificial layers; forming a preliminary blocking pattern by performing an epitaxy process from the side surfaces of the sacrificial layers in the recess regions; forming a charge storage pattern by performing an epitaxy process from a side surface of the preliminary blocking pattern in the recess regions; sequentially forming a tunneling layer and a channel layer in the hole; forming trenches to penetrate through the molded structure; removing the sacrificial layers exposed by the trenches; forming a blocking pattern by oxidizing the preliminary blocking pattern, exposed by removing the sacrificial layers; and forming gate layers to cover the blocking pattern and between the interlayer insulating layers. One side surface of the tunneling layer is in contact with the channel layer, and the other side surface of the tunneling layer is in contact with the interlayer insulating layers and the charge storage pattern. An upper surface or a lower surface of the charge storage pattern is coplanar with an upper surface or a lower surface of the blocking pattern. BRIEF DESCRIPTION OF THE DRAWINGS Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which: FIG. 1 is a plan view illustrating a semiconductor device according to example embodiments. FIG. 2 is a cross-sectional view illustrating a semiconductor device according to example embodiments. FIGS. 3A to 3C are partially enlarged cross-sectional views illustrating various examples of a semiconductor device according to example embodiments. FIG. 4 is a cross-sectional view of a semiconductor device according to example embodiments. FIG. 5 is a cross-sectional view of a semiconductor de