US-12621990-B2 - Split gate non-volatile memory cells, HV and logic devices with FINFET structures, and method of making same

US12621990B2US 12621990 B2US12621990 B2US 12621990B2US-12621990-B2

Abstract

A method of forming memory cells, high voltage devices and logic devices on fins of a semiconductor substrate's upper surface, and the resulting memory device formed thereby. The memory cells are formed on a pair of the fins, where the floating gate is disposed between the pair of fins, the word line gate wraps around the pair of fins, the control gate is disposed over the floating gate, and the erase gate is disposed over the pair of fins and partially over the floating gate. The high voltage devices include HV gates that wrap around respective fins, and the logic devices include logic gates that are metal and wrap around respective fins.

Inventors

Guo Xiang Song
Chunming Wang
Leo Xing
Xian Liu
Nhan Do

Assignees

SILICON STORAGE TECHNOLOGY, INC.

Dates

Publication Date: 20260505
Application Date: 20230130
Priority Date: 20201030

Claims (13)

1 . A memory device, comprising: a semiconductor substrate having an upper surface with a plurality of fins, wherein each of the fins extends upwardly and includes first and second side surfaces that oppose each other and that terminate in a top surface; a memory cell formed on first and second fins of the plurality of fins, comprising: a first channel region extending along the top surface and first and second side surfaces of the first fin from a source region of the first fin to a first drain region of the first fin for current flow between the source region of the first fin and the first drain region of the first fin, a second channel region extending along the top surface and first and second side surfaces of the first fin from the first drain region of the first fin to a second drain region of the first fin for current flow between the first drain region of the first fin and the second drain region of the first fin, a third channel region extending along the top surface and first and second side surfaces of the second fin from a source region of the second fin to a first drain region of the second fin for current flow between the source region of the second fin and the first drain region of the second fin, a fourth channel region extending along the top surface and first and second side surfaces of the second fin from the first drain region of the second fin to a second drain region of the second fin for current flow between the first drain region of the second fin and the second drain region of the second fin, a floating gate disposed between the first and second fins and extending along a first portion of the first channel region and a first portion of the third channel region, a control gate that extends along and is insulated from the floating gate, an erase gate having a first portion laterally adjacent to the floating gate and a second portion that is disposed over the floating gate, and a word line gate that extends along the second channel region and the fourth channel region, wherein the word line gate extends along and is insulated from the first and second side surfaces and the top surface of the first and second fins for controlling a conductivity of the second channel region from the first drain region to the second drain region of the first fin and for controlling a conductivity of the fourth channel region from the first drain region to the second drain region of the second fin; a high voltage (HV) device formed on a third fin of the plurality of fins, comprising: a HV channel region extending along the top surface and first and second side surfaces of the third fin from a HV source region of the third fin to a HV drain region of the third fin for current flow between the HV source region of the third fin and the HV drain region of the third fin, and a HV gate that extends along the HV channel region, wherein the HV gate extends along and is insulated from the first and second side surfaces and the top surface of the third fin; and a logic device formed on a fourth fin of the plurality of fins, comprising: a logic channel region extending along the top surface and first and second side surfaces of the fourth fin from a logic source region of the fourth fin to a logic drain region of the fourth fin for current flow between the logic source region of the fourth fin and the logic drain region of the fourth fin, and a logic gate that extends along the logic channel region, wherein the logic gate extends along and is insulated from the first and second side surfaces and the top surface of the fourth fin.
2 . The memory device of claim 1 , wherein the first portion of the erase gate extends along and is insulated from the top surfaces of the first and second fins.
3 . The memory device of claim 2 , wherein the first portion of the erase gate extends along and is insulated from a second portion of the first channel region and a second portion of the third channel region.
4 . The memory device of claim 1 , wherein the erase gate includes a notch facing an upper edge of the floating gate.
5 . The memory device of claim 1 , wherein the first and second fins are taller than the third and fourth fins.
6 . The memory device of claim 1 , wherein the logic gate includes a metal material, and wherein the logic gate is insulated from the first and second side surfaces and the top surface of the fourth fin by a high K insulation material.
7 . The memory device of claim 6 , wherein the floating gate, the word line gate, the control gate, the erase gate and the HV gate each include polysilicon material.
8 . The memory device of claim 1 , wherein the floating gate is disposed adjacent to the second side surface of the first fin for controlling a conductivity of a portion of the first channel region extending along the second side surface of the first fin, and wherein the floating gate is not disposed adjacent to the first side surface of the first fin.
9 . The memory device of claim 8 , wherein the floating gate is disposed adjacent to the first side surface of the second fin for controlling a conductivity of a portion of the third channel region extending along the first side surface of the second fin, and wherein the floating gate is not disposed adjacent to the second side surface of the second fin.
10 . A method of forming a memory device, comprising: forming a plurality of fins in an upper surface of a semiconductor substrate, wherein each of the fins extends upwardly and includes first and second side surfaces that oppose each other and that terminate in a top surface; and forming a memory cell on first and second fins of the plurality of fins, a high voltage (HV) device on a third fin of the plurality of fins, and a logic device on a fourth fin of the plurality of fins, by: forming a floating gate between the first and second fins; forming a control gate over and insulated from the floating gate; forming a layer of conductive material over the first fin, the second fin, the third fin and the fourth fin, wherein the layer of conductive material is polysilicon; selectively removing portions of the layer of conductive material, leaving: a word line gate as a first remaining portion of the layer of conductive material over the first and second fins, an erase gate as a second remaining portion of the layer of conductive material over the first and second fins, wherein the control gate is disposed between the word line gate and the erase gate, a HV gate as a third remaining portion of the layer of conductive material over the third fin, and a dummy gate as a fourth remaining portion of the layer of conductive material over the fourth fin; forming a source region in the first fin adjacent the erase gate; forming a first drain region in the first fin adjacent the word line gate; forming a second drain region in the first fin between the word line gate and the control gate, wherein a first channel region of the first fin extends along the top surface and the first and second side surfaces of the first fin from the source region of the first fin to the second drain region of the first fin, and wherein a second channel region of the first fin extends along the top surface and the first and second side surfaces of the first fin from the first drain region of the first fin to the second drain region of the first fin, wherein the floating gate is disposed adjacent to the second side surface of the first fin for controlling a conductivity of a portion of the first channel region extending along the second side surface of the first fin, and wherein the floating gate is not disposed adjacent to the first side surface of the first fin; forming a source region in the second fin adjacent the erase gate; forming a first drain region in the second fin adjacent the word line gate; forming a second drain region in the second fin between the word line gate and the control gate, wherein a first channel region of the second fin extends along the top surface and the first and second side surfaces of the second fin from the source region of the second fin to the second drain region of the second fin, and wherein a second channel region of the second fin extends along the top surface and the first and second side surfaces of the second fin from the first drain region of the second fin to the second drain region of the second fin, wherein the floating gate is disposed adjacent to the first side surface of the second fin for controlling a conductivity of a portion of the first channel region extending along the first side surface of the second fin, and wherein the floating gate is not disposed adjacent to the second side surface of the second fin; wherein the word line gate wraps around the first fin such that the word line gate extends along and is insulated from the top and opposing side surfaces of the first fin for controlling a conductivity of the second channel region of the first fin from the first drain region of the first fin to the second drain region of the first fin; wherein the word line gate wraps around the second fin such that the word line gate extends along and is insulated from the top and opposing side surfaces of the second fin for controlling a conductivity of the second channel region of the second fin from the first drain region of the second fin to the second drain region of the second fin; forming source and drain regions in the third fin adjacent the HV gate, wherein a channel region of the third fin extends along the top surface and the first and second side surfaces of the third fin from the source region of the third fin to the drain region of the third fin; forming source and drain regions in the fourth fin adjacent the dummy gate, wherein a channel region of the fourth fin extends along the top surface and the first and second side surfaces of the fourth fin from the source region of the fourth fin to the drain region of the fourth fin; and replacing the dummy gate with a logic gate formed of metal while maintaining the HV gate as the third remaining portion of the layer of conductive material.
11 . The method of claim 10 , wherein: the HV gate wraps around the third fin such that the HV gate extends along and is insulated from the top surface and the first and second side surfaces of the third fin; and the logic gate wraps around the fourth fin such that the logic gate extends along and is insulated from the top surface and the first and second side surfaces of the fourth fin.
12 . The method of claim 10 , wherein: the plurality of fins further includes fifth and sixth fins, the fourth fin is disposed between the fifth and sixth fins, the fourth fin is separated from the fifth fin by a first distance, the fourth fin is separated from the sixth fin by the first distance, the first fin is separated from the second fin by a second distance, the second distance is greater than the first distance.
13 . The method of claim 12 , wherein: the plurality of fins further includes seventh and eighth fins, the third fin is disposed between the seventh and eighth fins, the third fin is separated from the seventh fin by a third distance, the third fin is separated from the eighth fin by the third distance, the second distance is greater than the third distance.

Description

PRIORITY CLAIM This patent application is a divisional application of Ser. No. 17/152,441, filed Jan. 19, 2021, which claims priority to Chinese Patent Application No. 202011193113.X, filed on Oct. 30, 2020, entitled “Split Gate Non-volatile Memory Cells, HV And Logic Devices With FINFET Structures, And Method Of Making Same.” FIELD OF INVENTION The present invention relates to non-volatile flash memory cell arrays, high voltage devices, and logic devices, all formed on the same semiconductor substrate. BACKGROUND OF THE INVENTION Split gate non-volatile memory devices are well known in the art. For example, U.S. Pat. No. 7,927,994, which is incorporated herein by reference, discloses a split gate non-volatile memory cell. FIG. 1 illustrates an example of such a split gate memory cell formed on a semiconductor substrate 110. Source and drain regions 112 and 113 are formed as diffusion regions in substrate 110, and define a channel region 114 of the substrate 110 there between. The memory cell includes four conductive gates: a floating gate 115 disposed over and insulated from a first portion of the channel region 114 and a portion of the source region 112, a control gate (also called a coupling gate) 116 disposed over and insulated from the floating gate 115, an erase gate 117 disposed over and insulated from the source region 112, and a select gate (also called a word line gate) 118 disposed over and insulated from a second portion of the channel region 114. A conductive contact 119 can be formed to electrically connect to the drain region 113. Because the channel region 114 is formed along the planar surface of the semiconductor substrate, as device geometries get smaller, so too does total area (e.g. width) of the channel region. This reduces the current flow between the source and drain regions, requiring, among other things, more sensitive sense amplifiers to detect the state of the memory cell. Because the problem of shrinking the lithography size thereby reducing the channel width affects all semiconductor devices, a Fin-FET type of structure has been proposed. In a Fin-FET type of structure, a fin shaped member of semiconductor material connects the source to the drain regions. The fin shaped member has two side surfaces extending up and terminating in a top surface. Current from the source region to the drain region can then flow along the two side surfaces and the top surface. Thus, the width of the channel region is increased, thereby increasing the current flow. However, the width of the channel region is increased without sacrificing more semiconductor real estate by “folding” the channel region into two side surfaces and the top surface, thereby reducing the “footprint” of the channel region. Non-volatile memory cells using such Fin-FETs have been disclosed, where the floating gate and the select gate wrap around the top surface and two side surfaces of the fin shaped member. Some examples of prior art Fin-FET non-volatile memory structures (although the number and configuration of the gates varies from the above described planar example in FIG. 1) include U.S. Pat. Nos. 7,423,310, 7,410,913, 8,461,640, 9,985,042, and 10,468,428. It has also been proposed to form logic devices on fin shaped members. See for example U.S. Pat. Nos. 9,972,630 and 10,312,247. However, what is needed is an improved technique to form FinFET memory cells, FinFET logic devices and FinFET HV (high voltage) devices on the same substrate of a memory device. BRIEF SUMMARY OF THE INVENTION A memory device includes: a semiconductor substrate having an upper surface with a plurality of fins, wherein each of the fins extends upwardly and includes first and second side surfaces that oppose each other and that terminate in a top surface; a memory cell formed on first and second fins of the plurality of fins, comprising: a first channel region extending along the top surface and first and second side surfaces of the first fin between a source region of the first fin and a first drain region of the first fin,a second channel region extending along the top surface and first and second side surfaces of the first fin between the first drain region of the first fin and a second drain region of the first fin,a third channel region extending along the top surface and first and second side surfaces of the second fin between a source region of the second fin and a first drain region of the second fin,a fourth channel region extending along the top surface and first and second side surfaces of the second fin between the first drain region of the second fin and a second drain region of the second fin,a floating gate disposed between the first and second fins and extending along a first portion of the first channel region and a first portion of the third channel region,a control gate that extends along and is insulated from the floating gate,an erase gate having a first portion laterally adjacent to the floating gate and a second portion th