US-12621991-B2 - Semiconductor structure and method of forming the same

US12621991B2US 12621991 B2US12621991 B2US 12621991B2US-12621991-B2

Abstract

A method of forming a semiconductor structure includes providing a substrate with an array region, a peripheral region, and a transition region between the array region and the peripheral region. A patterned floating gate layer is formed on the array region and the peripheral region, and a stacked layer is conformally formed on the substrate, wherein a recess is formed over the transition region. A photoresist layer is formed on the substrate, and the photoresist layer is patterned to form an array region pattern on the stacked layer of the array region, wherein a portion of the photoresist layer remains at the bottom of the recess, and a recess pattern is formed. The array region pattern and the recess pattern are sequentially transferred to the stacked layer, the patterned floating gate layer and the substrate to form a plurality of arrays and a pair of blocking structures.

Inventors

Shun-Li Lan

Assignees

WINBOND ELECTRONICS CORP.

Dates

Publication Date: 20260505
Application Date: 20230608
Priority Date: 20230406

Claims (19)

1 . A semiconductor structure, comprising: a plurality of arrays disposed in an array region of a substrate; a peripheral structure disposed in a peripheral region of the substrate; and a pair of blocking structures disposed in a transition region of the substrate and comprising a portion of the substrate, wherein the transition region is disposed between the array region and the peripheral region, wherein the arrays comprise: a bottom formed by the substrate; a tunneling dielectric layer formed on the bottom; and a conductive layer formed on the tunneling dielectric layer, wherein a top surface of the pair of blocking structures is level with a top surface of the bottom.
2 . The semiconductor structure as claimed in claim 1 , wherein a trench depth between the blocking structures is greater than a trench depth between the arrays.
3 . The semiconductor structure as claimed in claim 2 , wherein the trench depth between the blocking structures is from about 200 nm to about 300 nm.
4 . The semiconductor structure as claimed in claim 2 , wherein the trench depth between the arrays is from about 100 nm to about 200 nm.
5 . The semiconductor structure as claimed in claim 1 , wherein a bottom width of the pair of blocking structures is from about 450 nm to about 550 nm.
6 . The semiconductor structure as claimed in claim 1 , further comprising: a dielectric layer disposed on the substrate and covering the arrays, the peripheral structure, and the pair of blocking structures; a ground contact penetrating the dielectric layer and contacting a top surface of the pair of blocking structures; and a pair of source/drain contacts in contact with a top surface of the peripheral structure.
7 . The semiconductor structure as claimed in claim 1 , wherein a top surface of the pair of blocking structures is lower than a top surface of the arrays.
8 . The semiconductor structure as claimed in claim 1 , further comprising: another pair of blocking structures disposed in the transition region of the substrate and adjacent to the pair of blocking structures.
9 . The semiconductor structure as claimed in claim 1 , wherein the peripheral region surrounds the array region, and a space between the array region and the peripheral region is a constant value.
10 . A method of forming the semiconductor structure as claimed in claim 1 , comprising: providing a substrate with an array region, a peripheral region, and a transition region between the array region and the peripheral region; forming a patterned floating gate layer on the array region and the peripheral region; conformally forming a stacked layer on the substrate, thereby forming a recess over the transition region; forming a photoresist layer on the substrate and filling the recess with the photoresist layer; patterning the photoresist layer to form an array region pattern on the stacked layer of the array region, wherein a portion of the photoresist layer remains at a bottom of the recess, thereby forming a recess pattern; and sequentially transferring the array region pattern and the recess pattern to the stacked layer, the patterned floating gate layer, and the substrate to form a plurality of arrays in the array region and to form a pair of blocking structures in the transition region.
11 . The method as claimed in claim 10 , wherein sequentially transferring the array region pattern and the recess pattern to the stacked layer, the patterned floating gate layer, and the substrate further comprises: using the array region pattern and the recess pattern as a mask and etching a first portion of the stacked layer to form a patterned mandrel layer; removing the array region pattern and the recess pattern; forming a plurality of sidewall spacers on sidewalls of the patterned mandrel layer; removing the patterned mandrel layer; and using the sidewall spacers as a mask, sequentially etching a second portion of the stacked layer, the patterned floating gate layer, and the substrate, thereby forming the arrays and the pair of blocking structures.
12 . The method as claimed in claim 11 , wherein after removing the patterned mandrel layer, the method further comprises: forming a mask layer on the substrate and covering the sidewall spacers; forming a peripheral region pattern on the mask layer of the peripheral region; and transferring the peripheral region pattern to the mask layer and exposing the sidewall spacers, wherein while using the sidewall spacers as the mask, sequentially etching the second portion of the stacked layer, the patterned floating gate layer, and the substrate, the peripheral region pattern correspondingly forms a peripheral structure in the peripheral region.
13 . The method as claimed in claim 10 , wherein after forming the arrays and the pair of blocking structures, the method further comprises: conformally forming a liner covering sidewalls of the arrays and the pair of blocking structures; forming a dielectric layer to fill trenches between the arrays and to fill trenches between the blocking structures; performing an annealing process; and forming a ground contact penetrating the dielectric layer until contacting a top surface of the pair of blocking structures.
14 . The method as claimed in claim 10 , wherein conformally forming the stacked layer further comprises: forming a protective layer on the substrate; forming a conductor layer on the protective layer; forming a mandrel layer on the conductor layer; forming a stop layer on the mandrel layer; and forming an anti-reflection layer on the stop layer, wherein the anti-reflection layer is in direct contact with the recess pattern.
15 . The method as claimed in claim 10 , wherein the patterned floating gate layer has an opening between the array region and the peripheral region of the substrate, and the aspect ratio of the opening is greater than 0.13.
16 . The method as claimed in claim 10 , wherein forming the patterned floating gate layer further comprises: forming a dummy structure in the transition region of the substrate, such that conformally forming the stacked layer further comprises forming another recess over the transition region of the substrate, wherein during the patterning of the photoresist layer, another portion of the photoresist layer remains at a bottom of the other recess, thereby forming another recess pattern, wherein while sequentially transferring the array region pattern and the recess pattern to the stacked layer, the patterned floating gate layer, and the substrate, the other recess pattern correspondingly forms another pair of blocking structures in the transition region.
17 . The method as claimed in claim 10 , wherein forming the patterned floating gate layer further comprises: forming a tunneling dielectric layer on the substrate; forming a conductive layer on the tunneling dielectric layer; and performing a patterning process to form the patterned floating gate layer.
18 . The method as claimed in claim 17 , wherein forming the conductive layer is an in-situ doping process.
19 . The method as claimed in claim 10 , wherein an opening width of the recess is from about 30 nm to about 40 nm.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This Application claims priority of Taiwan Patent Application No. 112112838 filed on Apr. 6, 2023, the entirety of which is incorporated by reference herein. BACKGROUND OF THE INVENTION Field of the Invention The present disclosure relates to a semiconductor process, and in particular to a method of forming a blocking structure. Description of the Related Art The critical dimensions of memory elements are gradually being scaled down as development of those memory elements advances, and the challenge of lithography processing is gradually increasing. In a conventional lithography process, the reduction of critical dimensions includes the use of optical elements with larger numerical apertures, shorter exposure wavelengths, and the use of interface materials other than air (e.g., water immersion). As the resolution of lithography processes approaches its theoretical limit, vendors have taken approaches such as double-patterning to overcome the optical limit and increase the integration of memory elements. However, during the process of forming a memory device, a doping path may be formed in the transition region between the array region and the peripheral region, which may result in leakage current. Therefore, in order to lower the cost while maintaining the level of the product's performance, the industry still needs to improve the method of forming semiconductor structures to achieve the desired goal of maintaining the yield of the memory device. BRIEF SUMMARY OF THE INVENTION An embodiment of the present disclosure provides a method of forming a semiconductor structure. The method comprises: providing a substrate with an array region, a peripheral region, and a transition region between the array region and the peripheral region; forming a patterned floating gate layer on the array region and the peripheral region; conformally forming a stacked layer on the substrate, thereby forming a recess over the transition region; forming a photoresist layer on the substrate and filling it into the recess; patterning the photoresist layer to form an array region pattern on the stacked layer of the array region, wherein a portion of the photoresist layer remains at the bottom of the recess, thereby forming a recess pattern; and sequentially transferring the array region pattern and the recess pattern to the stacked layer, the patterned floating gate layer, and the substrate to form a plurality of arrays in the array region and a pair of blocking structures in the transition region. Another embodiment of the present disclosure provides a semiconductor structure, comprising a plurality of arrays, a peripheral structure, and a pair of blocking structures. The arrays are disposed in an array region of a substrate. The peripheral structure is disposed in a peripheral region of the substrate. The blocking structures are disposed in a transition region of the substrate and comprise a portion of the substrate. The transition region is disposed between the array region and the peripheral region. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 11 illustrate cross-sectional views of intermediate stages of forming the semiconductor structure according to some embodiments of the present disclosure; FIGS. 12 to 13 illustrate layout of the semiconductor structure according to some embodiments of the present disclosure; and FIGS. 14 to 16 illustrate cross-sectional views of intermediate stages of forming the semiconductor structure according to other embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION During the process of forming a conventional memory device, after the arrays and peripheral structure are formed, the damaged semiconductor structure is repaired by filling the corresponding trenches with dielectric material and performing an annealing process before proceeding to the subsequent process. However, during the annealing process, the dielectric material may be heated and expanded, thereby causing a pushing stress at the interface between the dielectric material and the substrate in the relative open region (e.g., in the transition region between the array region and the peripheral region). Further, the dopant (e.g., boron) in the array region diffuse along the interface between the dielectric material and the substrate into the peripheral structures in the peripheral region, thereby causing leakage current and reducing the electrical performance of the device. In other cases, the dopant in the peripheral region is subjected to an extrusion stress and diffuses into the arrays in the array region, which also causing leakage current and reducing the electrical performance of the device. By forming a blocking structure in the transition region, the embodiment of the present disclosure increases the contact area of the interface between the dielectric material and the substrate in the transition region, making it more difficult for the dopant to diffuse into the perip