US-12621992-B2 - Semiconductor memory device

US12621992B2US 12621992 B2US12621992 B2US 12621992B2US-12621992-B2

Abstract

A semiconductor memory device according to an embodiment includes a first member and a plurality of pillars. The first member includes a first portion which is arranged locally on an upper end side and intermittently in a second direction. The plurality of pillars include first to sixth pillars. The second pillar is adjacent to the first pillar. The third pillar faces a first region between the first and second pillars. The fourth pillar is adjacent to the third pillar. The fifth pillar faces a second region between the third and fourth pillars. The sixth pillar is adjacent to the fifth pillar. A first end of the first portion faces the first region. The first to third regions are positioned on an identical straight line. The third region is between the fifth and sixth pillars.

Inventors

Takaaki Kondo

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260505
Application Date: 20220314
Priority Date: 20210913

Claims (16)

1 . A semiconductor memory device, comprising: a base layer which extends in a first plane that intersects a first direction; a first conductive layer which is provided above the base layer in the first direction; a first member which extends in a second direction above the base layer in the first direction, and which divides the first conductive layer in a third direction that intersects the first direction and the second direction, the second direction intersecting the first direction; a second member which is aligned with the first member in the third direction, which extends in the second direction above the base layer in the first direction, and which divides the first conductive layer in the third direction; and a plurality of pillars which penetrate the first conductive layer in the first direction, and which form memory cells at intersections with the first conductive layer, wherein the first member includes a first portion which is arranged locally on an upper end side and intermittently in the second direction, the plurality of pillars include: a first pillar; a second pillar which is adjacent to the first pillar in the second direction on a side of the second direction of the first pillar; a third pillar which faces a first region in the third direction, the first region being between the first pillar and the second pillar; a fourth pillar which is adjacent to the third pillar in the second direction on a side of the second direction of the third pillar; a fifth pillar which faces a second region in the third direction, the second region being between the third pillar and the fourth pillar; and a sixth pillar which is adjacent to the fifth pillar in the second direction on a side of the second direction of the fifth pillar, the first pillar and the second pillar face the first member, a first end of the first portion faces the first region, the first region, the second region, and a third region are positioned on an identical straight line, the third region being between the fifth pillar and the sixth pillar, a fourth region which is substantially central to a length of the first portion in the second direction, which is substantially central between the first member and the second member in the third direction, and which is positioned on a straight line that joins at least two of the first region, the second region, and the third region, the plurality of pillars further include: a seventh pillar which faces the first member; an eighth pillar which is adjacent to the seventh pillar in the second direction on a side of the second direction of the seventh pillar, and which faces the first member; a ninth pillar which faces a fifth region in the third direction, the fifth region being between the seventh pillar and the eighth pillar; and a tenth pillar which is adjacent to the ninth pillar in the second direction on a side of the second direction of the ninth pillar, a second end of the first portion faces the fifth region, and the fourth region is positioned on a straight line which joins the fifth region and a sixth region between the ninth pillar and the tenth pillar.
2 . The semiconductor memory device according to claim 1 , wherein an angle formed by a line which connects a center of the first pillar and a center of the second pillar and a line which connects a center of the third pillar and the center of the first pillar as viewed from the first direction is a first angle, an angle formed by a line which connects the fourth region and the first region and a straight line which passes through the first region and goes along the second direction as viewed from the first direction is a second angle, and the first angle and the second angle are approximately identical.
3 . The semiconductor memory device according to claim 1 , wherein the plurality of pillars are arranged in an approximately linear symmetry with the first member interposed therebetween.
4 . The semiconductor memory device according to claim 1 , wherein the first member further includes a metallic element containing layer between the first portion and a portion other than the first portion.
5 . The semiconductor memory device according to claim 4 , wherein the first member includes the metallic element containing layer containing at least one of a metallic oxide and a metallic material contained in the first conductive layer between the first portion and a second portion which is below the first portion in the first direction.
6 . The semiconductor memory device according to claim 1 , wherein a width of the first portion in the third direction differs from a width of another portion of the first member in the third direction.
7 . The semiconductor memory device according to claim 1 , wherein the first member further includes: a second portion below the first portion in the first direction; and a third portion which differs from the first and second portions, the first portion includes an insulator, the second portion includes a first sub conductor and a first sub insulator, the first sub insulator being provided between the first sub conductor and the first conductive layer, and the third portion includes a second sub conductor and a second sub insulator, the second sub insulator being provided between the second sub conductor and the first conductive layer.
8 . The semiconductor memory device according to claim 1 , wherein the first portion is formed of an insulator.
9 . The semiconductor memory device according to claim 2 , wherein a distance between the center of the first pillar and the center of the second pillar as viewed from the first direction is a first distance, a distance between the center of the third pillar and the center of the first pillar as viewed from the first direction is a second distance, a length of the first portion in the second direction is a first length, a distance between the fourth region and the first region as viewed from the first direction is a third distance, and a ratio between the first distance and the second distance is approximately identical to a ratio between the first length and the third distance.
10 . A semiconductor memory device, comprising: a lower-layer conductive layer; a first conductive layer provided above the lower-layer conductive layer in the first direction; a first member which extends along a second direction above the lower-layer conductive layer in the first direction, and which divides the first conductive layer in a third direction that intersects the first direction and the second direction, the second direction intersecting the first direction; a second member which is aligned with the first member in the third direction, which extends in the second direction above the lower-layer conductive layer in the first direction, and which divides the first conductive layer in the third direction; and a plurality of pillars which penetrate the first conductive layer in the first direction, which include a semiconductor layer that is in contact with the lower-layer conductive layer, and which form memory cells at intersections with the first conductive layer, wherein the first member includes a first portion which penetrates the first conductive layer in the first direction and reaches the lower-layer conductive layer, and which is intermittently arranged in the second direction, the plurality of pillars include: a first pillar; a second pillar which is adjacent to the first pillar in the second direction on a side of the second direction of the first pillar; a third pillar which faces a first region in the third direction, the first region being between the first pillar and the second pillar; a fourth pillar which is adjacent to the third pillar in the second direction on a side of the second direction of the third pillar; a fifth pillar which faces a second region in the third direction, the second region being between the third pillar and the fourth pillar; and a sixth pillar which is adjacent to the fifth pillar in the second direction on a side of the second direction of the fifth pillar, the first pillar and the second pillar face the first member, a first end of the first portion faces the first region, the first region, the second region, and a third region are positioned on an identical straight line, the third region being between the fifth pillar and the sixth pillar, a fourth region which is substantially central to a length of the first portion in the second direction, which is substantially central between the first member and the second member in the third direction, and which is positioned on a straight line that joins at least two of the first region, the second region, and the third region, the plurality of pillars further include: a seventh pillar which faces the first member; an eighth pillar which is adjacent to the seventh pillar in the second direction on a side of the second direction of the seventh pillar, and which faces the first member; a ninth pillar which faces a fifth region in the third direction, the fifth region being between the seventh pillar and the eighth pillar; and a tenth pillar which is adjacent to the ninth pillar in the second direction on a side of the second direction of the ninth pillar, a second end of the first portion faces the fifth region, and the fourth region is positioned on a straight line which joins the fifth region and a sixth region between the ninth pillar and the tenth pillar.
11 . The semiconductor memory device according to claim 10 , wherein an angle formed by a line which connects a center of the first pillar and a center of the second pillar and a line which connects a center of the third pillar and the center of the first pillar as viewed from the first direction is a first angle, an angle formed by a line which connects the fourth region and the first region and a straight line which passes through the first region and goes along the second direction as viewed from the first direction is a second angle, and the first angle and the second angle are approximately identical.
12 . The semiconductor memory device according to claim 10 , wherein the plurality of pillars are arranged in an approximately linear symmetry with the first member interposed therebetween.
13 . The semiconductor memory device according to claim 10 , wherein the first member further includes a metallic element containing layer between the first portion and a portion other than the first portion.
14 . The semiconductor memory device according to claim 10 , wherein a width of the first portion in the third direction differs from a width of another portion of the first member in the third direction.
15 . The semiconductor memory device according to claim 10 , wherein the first portion includes an insulator, and a portion of the first member other than the first portion includes a sub conductor and a sub insulator, the sub insulator being provided between the sub conductor and the first conductive layer.
16 . The semiconductor memory device according to claim 10 , wherein the first portion is formed of an insulator.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-148487, filed Sep. 13, 2021, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a semiconductor memory device. BACKGROUND A NAND flash memory capable of storing data in a non-volatile manner is known. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device 1 according to a first embodiment. FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the semiconductor memory device 1 according to the first embodiment. FIG. 3 is a plane diagram showing an example of a planar layout of the memory cell array included in the semiconductor memory device 1 according to the first embodiment. FIG. 4 is a plane diagram showing an example of a planar layout of the memory cell array included in the semiconductor memory device 1 according to the first embodiment. FIG. 5 is a cross-sectional diagram taken along line V-V of FIG. 3, showing an example of a cross-sectional structure of the memory cell array included in the semiconductor memory device 1 according to the first embodiment. FIG. 6 is a cross-sectional diagram taken along line VI-VI of FIG. 5, showing an example of a cross-sectional structure of a memory pillar MP in the semiconductor memory device 1 according to the first embodiment. FIG. 7 shows an example of a planar layout of the memory cell array included in the semiconductor memory device 1 according to the first embodiment. FIG. 8 is a flowchart showing an example of a method of manufacturing the semiconductor memory device 1 according to the first embodiment. FIGS. 9 to 13 show examples of cross-sectional structures of the semiconductor memory device 1 during manufacturing according to the first embodiment. FIG. 14 shows an example of a planar structure of the semiconductor memory device 1 during manufacturing according to the first embodiment. FIG. 15 shows an example of a cross-sectional structure of the semiconductor memory device 1 during manufacturing according to the first embodiment. FIG. 16 shows an example of a planar structure of the semiconductor memory device 1 during manufacturing according to the first embodiment. FIG. 17 shows an example of a cross-sectional structure of the semiconductor memory device 1 during manufacturing according to the first embodiment. FIG. 18 shows an example of a planar structure of the semiconductor memory device 1 during manufacturing according to the first embodiment. FIGS. 19 to 20 show examples of cross-sectional structures of the semiconductor memory device 1 during manufacturing according to the first embodiment. FIG. 21 shows an example of a planar structure of the semiconductor memory device 1 during manufacturing according to the first embodiment. FIG. 22 shows an example of a planar layout of a memory cell array in a semiconductor memory device 1r according to a comparative example of the first embodiment. FIG. 23 shows an example of a planar layout of the memory cell array included in the semiconductor memory device 1 according to the first embodiment. FIG. 24 shows an example of a cross-sectional structure of the memory cell array in the semiconductor memory device 1 according to a modification of the first embodiment. FIG. 25 shows an example of a planar layout of the memory cell array included in the semiconductor memory device 1 according to a modification of the first embodiment. FIG. 26 shows an example of a cross-sectional structure of the memory cell array in the semiconductor memory device 1 according to a modification of the first embodiment. FIG. 27 shows an example of a planar layout of a memory cell array included in a semiconductor memory device 1b according to a second embodiment. FIG. 28 shows an example of a planar layout of a memory cell array included in a semiconductor memory device 1c according to a third embodiment. FIG. 29 shows an example of a planar layout of a memory cell array included in a semiconductor memory device 1d according to a fourth embodiment. FIG. 30 is a cross-sectional diagram taken along line XXX-XXX of FIG. 29, showing an example of a cross-sectional structure of the memory cell array included in the semiconductor memory device 1d according to the fourth embodiment. FIG. 31 is a plane diagram showing an example of a planar layout of a memory cell array included in a semiconductor memory device 1e according to a fifth embodiment. DETAILED DESCRIPTION A semiconductor memory device according to an embodiment includes a base layer, a first conductive layer, a first member, and a plurality of pillars. The base layer extends in a first plane that intersects a first direction. The first conductive layer is provided above the base layer in the first direction. The first member extends in