US-12621993-B2 - Three-dimensional semiconductor memory device, electronic system including the same, and method of fabricating the same

Abstract

Disclosed are 3D semiconductor memory device, electronic systems including the same, and methods of fabricating the same. The 3D semiconductor memory device includes lower selection lines extending in a first direction on a substrate and spaced apart from each other in a second direction that is parallel to a top surface of the substrate and intersects the first direction, a middle stack structure including electrode layers and electrode interlayer dielectric layers that are alternately stacked on the lower selection lines, upper selection lines extending in the first direction on the middle stack structure and spaced apart from each other in the second direction, a first polishing stop layer disposed between the middle stack structure and the lower selection lines. The first polishing stop layer includes a material different from that of the electrode interlayer dielectric layers.

Inventors

• JAERYONG SIM
• DONGHYUCK JANG
• Jeehoon HAN

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20221114

Priority Date

20220128

Claims (20)

1. 1 . A three-dimensional semiconductor memory device, comprising: a plurality of lower selection lines disposed on a substrate and extending in a first direction, the lower selection lines being spaced apart from each other in a second direction that is parallel to a top surface of the substrate and intersects the first direction; a middle stack structure including a plurality of electrode layers and a plurality of electrode interlayer dielectric layers that are alternately stacked on the lower selection lines; a plurality of upper selection lines disposed on the middle stack structure and extending in the first direction, the upper selection lines being spaced apart from each other in the second direction; and a first polishing stop layer disposed between the middle stack structure and the lower selection lines, wherein the first polishing stop layer includes a material different from a material of the electrode interlayer dielectric layers, and the first polishing stop layer includes a dielectric material.
2. 2 . The device of claim 1 , wherein the lower selection lines include first, second, and third lower selection lines spaced apart from each other in the second direction, the upper selection lines include first, second, and third upper selection lines spaced apart from each other in the second direction, the first, second, and third lower selection lines respectively correspond to the first, second, and third upper selection lines, and the three-dimensional semiconductor memory device further comprises: a first lower separation pattern disposed between the first and second lower selection lines; and an upper separation pattern disposed between the first and second upper selection lines, wherein the first lower separation pattern and the upper separation pattern overlap each other and each extends in the first direction.
3. 3 . The device of claim 2 , wherein the first lower separation pattern has a first width, and the upper separation pattern has a second width smaller than the first width.
4. 4 . The device of claim 2 , wherein a top surface of the first lower separation pattern is coplanar with a top surface of the first polishing stop layer.
5. 5 . The device of claim 2 , wherein the first lower separation pattern and the upper separation pattern include a material the same as a material of the electrode interlayer dielectric layers.
6. 6 . The device of claim 2 , wherein the substrate includes a cell array region and a connection region, the three-dimensional semiconductor memory device further comprises a second lower separation pattern disposed on the connection region and between the second and third lower selection lines, the first lower separation pattern has a first width in the second direction, the second lower separation pattern has a second width in the second direction, and the second width is greater than the first width.
7. 7 . The device of claim 6 , further comprising a separation dielectric line disposed between the second and third lower selection lines and extending in the first direction, wherein the separation dielectric line extends in a third direction and is between the second and third upper selection lines, the third direction being perpendicular to the top surface of the substrate, and the separation dielectric line is in contact with a lateral surface of the second lower separation pattern.
8. 8 . The device of claim 2 , further comprising: a plurality of cell vertical semiconductor patterns that penetrate the upper selection lines, the middle stack structure, the first polishing stop layer, and the lower selection lines; and a dummy vertical semiconductor pattern that penetrates the upper selection lines, the middle stack structure, the first polishing stop layer, and the first lower separation pattern to be adjacent to the substrate.
9. 9 . The device of claim 1 , wherein the first polishing stop layer includes SiCN, and each of the electrode interlayer dielectric layers includes silicon oxide.
10. 10 . The device of claim 1 , wherein the middle stack structure includes a first middle stack structure and a second middle stack structure on the first middle stack structure, the three-dimensional semiconductor device further comprises a second polishing stop layer disposed between the first middle stack structure and the second middle stack structure, and the second polishing stop layer includes a material the same as a material of the first polishing stop layer.
11. 11 . The device of claim 1 , wherein the substrate includes a cell array region and a connection region, ends of the upper selection lines, ends of the electrode layers, and ends of the lower selection lines constitute a stepwise shape on the connection region, the three-dimensional semiconductor memory device further comprises: a planarized dielectric layer on the connection region, the planarized dielectric layer covering the ends of the upper selection lines, the ends of the electrode layers, and the ends of the lower selection lines; and a second polishing stop layer that covers the upper selection lines, wherein the second polishing stop layer includes a material the same as a material of the first polishing stop layer.
12. 12 . An electronic system, comprising: a semiconductor device that includes a peripheral circuit structure and a cell array structure on the peripheral circuit structure; an input/output pad electrically connected to the peripheral circuit structure; and a controller electrically connected through the input/output pad to the semiconductor device, the controller controlling the semiconductor device, wherein the cell array structure includes: a plurality of lower selection lines disposed on a substrate and extending in a first direction, the lower selection lines being spaced apart from each other in a second direction that is parallel to a top surface of the substrate and intersects the first direction; a middle stack structure including a plurality of electrode layers and a plurality of electrode interlayer dielectric layers that are alternately stacked on the lower selection lines; a plurality of upper selection lines disposed on the middle stack structure and extending in the first direction; and a first polishing stop layer disposed between the middle stack structure and the lower selection lines and including a material different from a material of the electrode interlayer dielectric layers, and the first polishing stop layer includes a dielectric material.
13. 13 . A three-dimensional semiconductor memory device, comprising: a plurality of lower selection lines disposed on a substrate and extending in a first direction, the lower selection lines being spaced apart from each other in a second direction that is parallel to a top surface of the substrate and intersects the first direction; a middle stack structure including a plurality of electrode layers and a plurality of electrode interlayer dielectric layers that are alternately stacked on the lower selection lines; a plurality of upper selection lines disposed on the middle stack structure and extending in the first direction, the upper selection lines being spaced apart from each other in the second direction; and a first polishing stop layer disposed between the middle stack structure and the lower selection lines, wherein the first polishing stop layer includes a material different from a material of the electrode interlayer dielectric layers, the lower selection lines include first, second, and third lower selection lines spaced apart from each other in the second direction, the upper selection lines include first, second, and third upper selection lines spaced apart from each other in the second direction, the first, second, and third lower selection lines respectively correspond to the first, second, and third upper selection lines, and the three-dimensional semiconductor memory device further comprises: a first lower separation pattern disposed between the first and second lower selection lines; and an upper separation pattern disposed between the first and second upper selection lines, wherein the first lower separation pattern and the upper separation pattern overlap each other and each extends in the first direction.
14. 14 . The device of claim 13 , wherein the first lower separation pattern has a first width, and the upper separation pattern has a second width smaller than the first width.
15. 15 . The device of claim 13 , wherein a top surface of the first lower separation pattern is coplanar with a top surface of the first polishing stop layer.
16. 16 . The device of claim 13 , wherein the first lower separation pattern and the upper separation pattern include a material the same as a material of the electrode interlayer dielectric layers.
17. 17 . The device of claim 13 , wherein the substrate includes a cell array region and a connection region, the three-dimensional semiconductor memory device further comprises a second lower separation pattern disposed on the connection region and between the second and third lower selection lines, the first lower separation pattern has a first width in the second direction, the second lower separation pattern has a second width in the second direction, the second width is greater than the first width, the three-dimensional semiconductor memory device further comprises a separation dielectric line disposed between the second and third lower selection lines and extending in the first direction, the separation dielectric line extends in a third direction and is between the second and third upper selection lines, the third direction being perpendicular to the top surface of the substrate, and the separation dielectric line is in contact with a lateral surface of the second lower separation pattern.
18. 18 . The device of claim 13 , further comprising: a plurality of cell vertical semiconductor patterns that penetrate the upper selection lines, the middle stack structure, the first polishing stop layer, and the lower selection lines; and a dummy vertical semiconductor pattern that penetrates the upper selection lines, the middle stack structure, the first polishing stop layer, and the first lower separation pattern to be adjacent to the substrate.
19. 19 . The device of claim 13 , wherein the middle stack structure includes a first middle stack structure and a second middle stack structure on the first middle stack structure, the three-dimensional semiconductor device further comprises a second polishing stop layer disposed between the first middle stack structure and the second middle stack structure, and the second polishing stop layer includes a material the same as a material of the first polishing stop layer.
20. 20 . The device of claim 13 , wherein the substrate includes a cell array region and a connection region, ends of the upper selection lines, ends of the electrode layers, and ends of the lower selection lines constitute a stepwise shape on the connection region, the three-dimensional semiconductor memory device further comprises: a planarized dielectric layer on the connection region, the planarized dielectric layer covering the ends of the upper selection lines, the ends of the electrode layers, and the ends of the lower selection lines; and a second polishing stop layer that covers the upper selection lines, and the second polishing stop layer includes a material the same as a material of the first polishing stop layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION This U.S. nonprovisional application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0012993, filed on Jan. 28, 2022, in the Korean Intellectual Property Office, the disclosure of which is herein incorporated by reference in its entirety. TECHNICAL FIELD The present inventive concept relates to a semiconductor device, an electronic system including the same, and a method of fabricating the same, and more particularly, to a three-dimensional semiconductor memory device with enhanced reliability and increased integration, an electronic system including the same, and a method of fabricating the same. DISCUSSION OF RELATED ART Because integration of a semiconductor device is an important factor in determining a price of an electronic product, semiconductor devices with high integration may be required to meet the rising demand for high performance and low cost electronic products by consumers. Integration of typical two-dimensional (2D) or planar semiconductor devices is primarily determined by the area occupied by a unit memory cell, such that it is greatly influenced by the level of technology for forming fine patterns. However, the extremely expensive processing equipment needed to increase pattern fineness may set a practical limitation on increasing the integration of the two-dimensional (2D) or planar semiconductor devices. Therefore, three-dimensional (3D) semiconductor memory devices including three-dimensionally arranged memory cells have been proposed to overcome the above limitations. SUMMARY Embodiments of the present inventive concept provide a three-dimensional semiconductor memory device and an electronic system with enhanced reliability and increased integration. Embodiments of the present inventive concept also provide a method of fabricating a three-dimensional semiconductor memory device with enhanced productivity. According to an embodiment of the present inventive concept, a three-dimensional semiconductor memory device may include: a plurality of lower selection lines disposed on a substrate and extending in a first direction, the lower selection lines being spaced apart from each other in a second direction that is parallel to a top surface of the substrate and intersects the first direction; a middle stack structure including a plurality of electrode layers and a plurality of electrode interlayer dielectric layers that are alternately stacked on the lower selection lines; a plurality of upper selection lines disposed on the middle stack structure and extending in the first direction, the upper selection lines being spaced apart from each other in the second direction; and a first polishing stop layer disposed between the middle stack structure and the lower selection lines. The first polishing stop layer may include a material different from a material of the electrode interlayer dielectric layers. According to an embodiment of the present inventive concept, a three-dimensional semiconductor memory device may include a peripheral circuit structure and a cell array structure on the peripheral circuit structure. The cell array structure may include: a substrate including a cell array region and a connection region that are side by side in a first direction; a source structure disposed on the substrate; a plurality of lower selection lines disposed on the source structure and extending in the first direction, the lower selection lines being spaced apart from each other in a second direction that is parallel to a top surface of the substrate and intersects the first direction; a middle stack structure including a plurality of electrode layers and a plurality of electrode interlayer dielectric layers that are alternately stacked on the lower selection lines; a plurality of upper selection lines disposed on the middle stack structure and extending in the first direction, the upper selection lines being spaced apart from each other in the second direction; a first polishing stop layer disposed between the middle stack structure and the lower selection lines; a planarized dielectric layer disposed on the connection region and covering ends of the lower selection lines, an end of the first polishing stop layer, an end of the middle stack structure, and ends of the upper selection lines; a plurality of cell vertical semiconductor patterns disposed on the cell array region and adjacent to the substrate, the cell vertical semiconductor patterns penetrating the upper selection lines, the middle stack structure, the first polishing stop layer, the lower selection lines, and the source structure; and a plurality of bit-line pads disposed on corresponding cell vertical semiconductor patterns. Each of the first polishing stop layer and the electrode interlayer dielectric layers may include silicon oxide. A silicon atomic concentration of the first polishing stop layer may be greater than a silicon atomic concentration of the electrode