US-12621994-B2 - Semiconductor device and manufacturing method of semiconductor device

Abstract

A semiconductor device includes: a first gate structure including a cell region and a contact region; a channel structure located in the cell region of the first gate structure; and a supporter located in the contact region of the first gate structure.

Inventors

• Chul Young Kim
• Ji Yeon BAEK
• Kyung Sung YUN
• Kyung Jin Lee
• Sul Gi JUNG

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260505

Application Date

20230517

Priority Date

20221212

Claims (20)

1. 1 . A semiconductor device comprising: a first gate structure including a cell region and a contact region; a channel structure located in the cell region of the first gate structure; and a supporter located in the contact region of the first gate structure, wherein the supporter comprises: a first oxide layer; a first nitride layer in the first oxide layer; and a second oxide layer in the first nitride layer, and wherein the supporter comprises a bowing shape.
2. 2 . The semiconductor device of claim 1 , wherein the second oxide layer includes a void therein.
3. 3 . The semiconductor device of claim 1 , wherein the supporter has a first width at a first level, has a second width at a second level, and has a third width at a third level located between the first level and the second level, the third width being greater than the first width and the second width.
4. 4 . The semiconductor device of claim 1 , wherein the supporter has substantially at least one of a circular shape, an elliptical shape, a polygonal shape, and a line shape in a plane.
5. 5 . The semiconductor device of claim 1 , further comprising: a second gate structure; and a slit structure located between the first gate structure and the second gate structure, wherein the slit structure comprises: a third oxide layer; a second nitride layer in the third oxide layer; and a fourth oxide layer in the second nitride layer, and wherein the slit structure extends from the cell region to the contact region.
6. 6 . The semiconductor device of claim 5 , wherein the slit structure has a bowing shape in a cross section.
7. 7 . The semiconductor device of claim 5 , wherein at least one of the third oxide layer, the second nitride layer, and the fourth oxide layer includes a protrusion on an outer wall thereof.
8. 8 . The semiconductor device of claim 5 , wherein the slit structure includes a source contact plug located in the fourth oxide layer.
9. 9 . The semiconductor device of claim 8 , wherein the source contact plug includes a void therein.
10. 10 . A semiconductor device comprising: a first gate structure including a cell region and a contact region; a channel structure located in the cell region of the first gate structure; and a supporter located in the contact region of the first gate structure, wherein the supporter comprises: a first sealing layer; a first stressor in the first sealing layer; and a second sealing layer in the first stressor, and wherein the supporter has a first width at a first level, has a second width at a second level, and has a third width at a third level located between the first level and the second level, the third width being greater than the first width and the second width.
11. 11 . The semiconductor device of claim 10 , wherein the first stressor includes nitride, a low-k material, or a high-k material, or a combination thereof.
12. 12 . The semiconductor device of claim 10 , wherein the first stressor includes silicon carbon nitride (SiCN), silicon boron nitride (SiBN), boron nitride (BN), aluminum oxide (AlO x ), or hafnium oxide (HfO x ), or a combination thereof.
13. 13 . A semiconductor device, comprising: a first gate structure including a cell region and a contact region; a channel structure located in the cell region of the first gate structure; and a supporter located in the contact region of the first gate structure, wherein the supporter comprises: a first sealing layer; a first stressor in the first sealing layer; and a second sealing layer in the first stressor, and wherein the first sealing layer has a greater thickness than the second sealing layer.
14. 14 . A semiconductor device, comprising: a first gate structure including a cell region and a contact region; a channel structure located in the cell region of the first gate structure; and a supporter located in the contact region of the first gate structure, wherein the supporter comprises: a first sealing layer; a first stressor in the first sealing layer; and a second sealing layer in the first stressor; a second gate structure; and a slit structure located between the first gate structure and the second gate structure, wherein the slit structure comprises: a first insulating layer; a second stressor in the first insulating layer; and a second insulating layer in the second stressor, and wherein the slit structure extends from the cell region to the contact region.
15. 15 . The semiconductor device of claim 14 , wherein the slit structure includes a source contact plug located in the second insulating layer.
16. 16 . The semiconductor device of claim 14 , wherein at least one of the first insulating layer, the second stressor, and the second insulating layer includes a protrusion on an outer wall thereof.
17. 17 . A manufacturing method of a semiconductor device, the manufacturing method comprising: forming a stack including a cell region and a contact region; forming a first opening having a bowing shape in the contact region of the stack; and forming, in the first opening, a supporter including a first oxide layer, a first nitride layer, and a second oxide layer.
18. 18 . The manufacturing method of claim 17 , wherein the forming of the supporter comprises: forming the first oxide layer in the first opening; forming the first nitride layer in the first oxide layer; and forming the second oxide layer in the first nitride layer.
19. 19 . The manufacturing method of claim 18 , wherein the second oxide layer includes a void therein.
20. 20 . The manufacturing method of claim 17 , further comprising: forming, in the stack, a second opening extending from the cell region to the contact region and having a bowing shape; and forming, in the second opening, a slit structure including a third oxide layer, a second nitride layer in the third oxide layer, and a fourth oxide layer in the second nitride layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2022-0172779 filed on Dec. 12, 2022, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. BACKGROUND 1. Technical Field Embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a semiconductor device and a manufacturing method of the semiconductor device. 2. Related Art The degree of integration of a semiconductor device is mainly determined by an area occupied by a unit memory cell. Recently, as the improvement in the degree of integration of a semiconductor device for forming memory cells in a single layer on a substrate reaches a limit, a three-dimensional semiconductor device for stacking memory cells on a substrate has been proposed. Furthermore, in order to improve the operational reliability of such a semiconductor device, various structures and manufacturing methods have been developed. SUMMARY In an embodiment, a semiconductor device may include: a first gate structure including a cell region and a contact region; a channel structure located in the cell region of the first gate structure; and a supporter located in the contact region of the first gate structure, wherein the supporter comprises: a first oxide layer; a first nitride layer in the first oxide layer; and a second oxide layer in the first nitride layer, and wherein the supporter comprises a bowing shape. In an embodiment, a semiconductor device may include: a first gate structure including a cell region and a contact region; a channel structure located in the cell region of the first gate structure; and a supporter located in the contact region of the first gate structure, wherein the supporter comprises: a first sealing layer; a first stressor in the first sealing layer; and a second sealing layer in the first stressor, and wherein the first stressor may apply a stress from the first sealing layer toward the second sealing layer. In an embodiment, a manufacturing method of a semiconductor device may include: forming a stack including a cell region and a contact region; forming a first opening having a bowing shape in the contact region of the stack; and forming, in the first opening, a supporter including a first oxide layer, a first nitride layer, and a second oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A, 1B, 1C, and FIG. 1D are diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. FIG. 2A, 2B, 2C, and FIG. 2D are diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. FIG. 3A, 3B, 3C, and FIG. 3D are diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. FIG. 4A, 4B, 4C, 4D, and FIG. 4E are diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. FIG. 5A, 5B, 5C, and FIG. 5D are diagrams for describing a manufacturing method of a semiconductor device in accordance with an embodiment. FIG. 6A and FIG. 6B are diagrams for describing a manufacturing method of a semiconductor device in accordance with an embodiment. FIG. 7A, 7B, and FIG. 7C are diagrams for describing a manufacturing method of a semiconductor device in accordance with an embodiment. DETAILED DESCRIPTION Various embodiments are directed to a semiconductor device having a stable structure and improved characteristics and a manufacturing method thereof. In an embodiment, by stacking memory cells in three dimensions, it is possible to improve the degree of integration of a semiconductor device. Furthermore, in an embodiment, it is possible to provide a semiconductor device having a stable structure and improved reliability. Hereafter, embodiments in accordance with the technical spirit of the present disclosure will be described with reference to the accompanying drawings. It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, but not used to define only the element itself or to mean a particular sequence. FIG. 1A to FIG. 1D are diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. FIG. 1A may be a plan view, FIG. 1B may be a cross-sectional view taken along line A-A′ in FIG. 1A, and FIG. 1C may be a cross-sectional view taken along line B-B′ in FIG. 1A. Referring to FIG. 1A to FIG. 1C, the semiconductor device may include gate structures GST, a channel structure CH, and a first supporter SP1. The semiconductor device may further include a second supporter SP2, a first slit structure SLS1, second slit structures SLS21 and SLS22, an interlayer dielectric layer 7, or a source structure 10, or a combination thereof. The gate structure GST may be locat