US-12621995-B2 - Nonvolatile memory device and method for fabricating the same

Abstract

A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

Inventors

• Soodoo Chae
• Myoungbum Lee
• HuiChang Moon
• Hansoo Kim
• JinGyun Kim
• Kihyun Kim
• Siyoung Choi
• Hoosung Cho

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20240122

Priority Date

20081203

Claims (20)

1. 1 . A three-dimensional semiconductor device comprising: a substrate including a first region and a second region; a stacked structure including a plurality of horizontal layers and a plurality of insulating layers alternately stacked on the substrate, the stacked structure having a staircase portion on the second region; a plurality of channel hole structures extending through the stacked structure on the first region, each of the plurality of channel hole structures including an active pattern and a charge storage layer; a plurality of bit lines electrically connected to the plurality of channel hole structures; and a plurality of dummy hole structures extending through the stacked structure on the second region, wherein the charge storage layer extends between the active pattern and ones of the plurality of horizontal layers, and wherein at least one of the dummy hole structures extends from an uppermost one of the horizontal layers to a lowermost one of the horizontal layers and is free of electrical connection with any bit lines.
2. 2 . The three-dimensional semiconductor device of claim 1 , wherein respective ones of the dummy hole structures penetrate all or some of the horizontal layers.
3. 3 . The three-dimensional semiconductor device of claim 1 , further comprising: a plurality of contact plugs on the second region and electrically connected to respective ones of the plurality of horizontal layers; and a plurality of conductive lines electrically connected to the plurality of contact plugs.
4. 4 . The three-dimensional semiconductor device of claim 3 , wherein the plurality of contact plugs have different respective vertical lengths on the second region, and wherein the vertical lengths increase with increasing distance from the first region.
5. 5 . The three-dimensional semiconductor device of claim 3 , wherein at least one of the plurality of dummy hole structures is located between adjacent ones of the contact plugs.
6. 6 . The three-dimensional semiconductor device of claim 3 , wherein the plurality of dummy hole structures are free of electrical connection with any conductive lines.
7. 7 . The three-dimensional semiconductor device of claim 1 , wherein each of the horizontal layers has an end portion on the second region, and wherein the end portions of the horizontal layers are horizontally spaced apart from each other.
8. 8 . The three-dimensional semiconductor device of claim 1 , wherein the plurality of dummy hole structures have different respective vertical lengths on the second region.
9. 9 . The three-dimensional semiconductor device of claim 1 , wherein the plurality of dummy hole structures have different respective vertical lengths on the second region, and wherein the vertical lengths decrease with increasing distance from the first region.
10. 10 . The three-dimensional semiconductor device of claim 1 , wherein the horizontal layers comprise conductive material on the first region and the second region.
11. 11 . The three-dimensional semiconductor device of claim 1 , further comprising a planarized dielectric layer covering the staircase portion of the stacked structure, wherein at least one of the plurality of dummy hole structures penetrates the staircase portion of the stacked structure.
12. 12 . A three-dimensional semiconductor device comprising: a substrate including a first region and a second region; a stacked structure including a plurality of horizontal layers and a plurality of insulating layers alternately stacked on the substrate, the stacked structure including a first portion on the first region and a second portion on the second region, the second portion of the stacked structure having a staircase portion on the second region; a plurality of channel hole structures extending through the first portion of the stacked structure on the first region; and a plurality of dummy hole structures extending through the second portion of the stacked structure on the second region, wherein the plurality of dummy hole structures include a first dummy hole structure which is disposed closest to the channel hole structures, wherein the first dummy hole structure has a top surface located at the same level as top surfaces of the channel hole structures, and wherein the plurality of dummy hole structures include a second dummy hole structure extending through a lowermost one of the plurality of horizontal layers on the second region.
13. 13 . The three-dimensional semiconductor device of claim 12 , further comprising a plurality of contact plugs on the second region and electrically connected to respective ones of the plurality of horizontal layers, wherein at least one of the plurality of dummy hole structures is located between adjacent ones of the contact plugs.
14. 14 . The three-dimensional semiconductor device of claim 13 , further comprising a plurality of conductive lines electrically connected to the plurality of contact plugs, wherein the plurality of dummy hole structures are free of electrical connection with any conductive lines.
15. 15 . The three-dimensional semiconductor device of claim 12 , wherein respective ones of the dummy hole structures penetrate all or some of the horizontal layers.
16. 16 . The three-dimensional semiconductor device of claim 12 , wherein each of the horizontal layers has an end portion on the second region, wherein the end portions of the horizontal layers are horizontally spaced apart from each other, and wherein respective ones of the plurality of dummy hole structures penetrate respective ones of the end portions of the horizontal layers.
17. 17 . The three-dimensional semiconductor device of claim 12 , wherein the plurality of dummy hole structures have different respective vertical lengths on the second region, and wherein a top surface of the second dummy hole structure is non-coplanar with the top surface of the first dummy hole structure.
18. 18 . The three-dimensional semiconductor device of claim 12 , wherein a bottom surface of the first dummy hole structure is coplanar with a bottom surface of the second dummy hole structure.
19. 19 . A three-dimensional semiconductor device comprising: a substrate including a first region and a second region; a stacked structure including a plurality of horizontal layers and a plurality of insulating layers alternately stacked on the substrate, the stacked structure having a staircase portion on the second region; a plurality of channel hole structures extending through the stacked structure on the first region; and a plurality of dummy hole structures extending through the stacked structure on the second region, the plurality of dummy hole structures comprising dielectric material, wherein at least one of the plurality of dummy hole structures penetrates the plurality of horizontal layers in the staircase portion of the stacked structure.
20. 20 . The three-dimensional semiconductor device of claim 19 , wherein the plurality of dummy hole structures include a first dummy hole structure that extends through a first non-zero number of the horizontal layers, and a second dummy hole structure that extends through a second non-zero number of the horizontal layers that is different from the first non-zero number.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a continuation application of and claims priority from U.S. patent application Ser. No. 17/870,037, filed on Jul. 21, 2022, which is a continuation application of and claims priority from U.S. patent application Ser. No. 17/517,137, filed on Nov. 2, 2021, now U.S. Pat. No. 11,871,571, which is a continuation application of and claims priority from U.S. patent application Ser. No. 17/497,417, filed on Oct. 8, 2021, which is a continuation application of and claims priority from U.S. patent application Ser. No. 16/708,482, filed on Dec. 10, 2019, now U.S. Pat. No. 11,387,249, which is a continuation application of and claims priority from U.S. patent application Ser. No. 15/634,597, filed on Jun. 27, 2017, now U.S. Pat. No. 10,546,872, which is a continuation application of and claims priority from U.S. patent application Ser. No. 14/973,182, filed on Dec. 17, 2015, now U.S. Pat. No. 9,735,170, which is a continuation application of and claims priority from U.S. patent application Ser. No. 14/027,599, filed on Sep. 16, 2013, now U.S. Pat. No. 9,245,839, which is a continuation application of and claims priority from U.S. patent application Ser. No. 12/592,869, filed on Dec. 3, 2009, now U.S. Pat. No. 8,541,831, which claims the benefit of Korean Patent Application Nos. 10-2008-0121886, filed on Dec. 3, 2008, and 10-2009-0016406, filed on Feb. 26, 2009, the entire contents of which are hereby incorporated by reference. BACKGROUND The present inventive concept relates to nonvolatile memory devices and methods for fabricating the same, and more particularly, to three-dimensional nonvolatile memory devices capable of reducing the resistance of gate electrodes and preventing process defects, and methods for fabricating the same. Nonvolatile memory devices can electrically erase and write (or program) data and can retain data even when the power supply is interrupted. Accordingly, the use of nonvolatile memory devices is increasing in various fields. Nonvolatile memory devices include various types of memory cell transistors. Nonvolatile memory devices are classified into NAND-type nonvolatile memory devices and a NOR-type nonvolatile memory device, depending on the cell array structures. The NAND-type nonvolatile memory device and the NOR-type nonvolatile memory device have the advantages and disadvantages of high integration and high operation speed. In particular, the NAND-type nonvolatile memory device is advantageous for high integration because it includes a cell string structure having a plurality of memory cell transistors connected in series. Also, the NAND-type nonvolatile memory device has a much higher data update speed than the NOR-type nonvolatile memory device because it uses an operation scheme of simultaneously changing data stored in a plurality of memory cell transistors. Due to such a high integration level and high update speed, the NAND-type nonvolatile memory device is widely used in portable electronic products requiring mass storage, such as digital cameras and MP3 players. Research is being conducted to facilitate and promote the advantages of NAND-type nonvolatile memory devices. Accordingly, a three-dimensional nonvolatile memory device is being developed. SUMMARY OF THE INVENTIVE CONCEPT Embodiments of the inventive concept provide three-dimensional nonvolatile memory devices capable of reducing the resistance of gate electrodes, and methods for fabricating the same. Embodiments of the inventive concept also provide three-dimensional nonvolatile memory devices capable of preventing process defects, and methods for fabricating the same. According to one aspect, the inventive concept is directed to a nonvolatile memory device including: a semiconductor substrate including a memory cell region and a contact region; a plurality of active pillars extending in the memory cell region perpendicular to the semiconductor substrate; a plurality of gate electrodes that intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate; and a plurality of supporters extending in the contact region perpendicular to the semiconductor substrate to penetrate at least one or more of the gate electrodes. In one embodiment, the supporters are formed of dielectric material or semiconductor material. In one embodiment, the supporters penetrate all or some of the gate electrodes. In one embodiment, the gate electrodes are stacked on the semiconductor substrate, with an interlayer dielectric therebetween, and the areas of the gate electrodes decrease with an increase in the distance from the semiconductor substrate. In one embodiment, the gate electrodes are stacked on the semiconductor substrate, with an interlayer dielectric therebetween; the upper gate electrode among the gate electrodes exposes an edge portion of the lower gate electrode; and the supporters are disposed at t