US-12621996-B2 - Semiconductor integrated circuit device and method of manufacturing the semiconductor integrated circuit device

US12621996B2US 12621996 B2US12621996 B2US 12621996B2US-12621996-B2

Abstract

The present disclosure relates to a semiconductor integrated circuit device and method of manufacturing the semiconductor integrated circuit device. A semiconductor integrated circuit device including a semiconductor substrate, a first transistor, an insulation interlayer and a second transistor. The first transistor formed on the semiconductor substrate. The first transistor includes a horizontal channel substantially parallel to a surface of the semiconductor substrate. The insulating interlayer formed on an upper surface of the semiconductor substrate. A contact hole formed through the insulating interlayer. The second transistor including a channel layer formed in the contact hole. Any one of a source and a drain of the second transistor are electrically connected to any one of electrodes of the first transistor.

Inventors

Ki Chang JEONG
Nam Kuk KIM

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260505
Application Date: 20220505
Priority Date: 20211215

Claims (20)

1 . A semiconductor integrated circuit device comprising: a semiconductor substrate; a first transistor over the semiconductor substrate, the first transistor including a horizontal channel substantially parallel to a surface of the semiconductor substrate; an insulating interlayer over the semiconductor substrate, the insulating interlayer including a contact hole through the insulating interlayer; and a second transistor including a channel layer in the contact hole, wherein any one of a source and a drain included in the second transistor is electrically connected to at least one electrode of the first transistor.
2 . The semiconductor integrated circuit device of claim 1 , wherein the second transistor comprises: a vertical gate over a sidewall of the contact hole; a gate insulation layer over a surface of the vertical gate and the sidewall of the contact hole; a vertical channel layer over a surface of the gate insulation layer and a bottom surface of the contact hole; and a first junction region in an upper region of the vertical channel layer, wherein at least a part of the vertical channel layer on the bottom surface of the contact hole is electrically connected to the at least one electrode of the first transistor to form a second junction region.
3 . The semiconductor integrated circuit device of claim 2 , wherein the second transistor further comprises a gate pad extended from the vertical gate along an upper surface of the insulating interlayer.
4 . The semiconductor integrated circuit device of claim 2 , wherein the second transistor further comprises a gap-filling insulation layer in a space surrounded by the vertical channel layer and the first junction region is arranged over the vertical channel layer and the gap-filling insulation layer.
5 . The semiconductor integrated circuit device of claim 1 , wherein the insulating interlayer comprises: a first insulating interlayer including the first transistor and a wiring connection configured to transmit an electrical signal to the first transistor; a second insulating interlayer over the first insulating interlayer, the second insulating interlayer including a first stack structure with a plurality of memory cells; and a third insulating interlayer over the second insulating interlayer, the third insulating interlayer including a second stack structure with a plurality of memory cells electrically connected with the first stack structure.
6 . The semiconductor integrated circuit device of claim 5 , wherein the contact hole is configured to pass through the first to third insulating interlayers to expose the at least one electrode of the first transistor.
7 . The semiconductor integrated circuit device of claim 5 , wherein the first insulating interlayer further comprises peripheral circuits configured to control the plurality of memory cells of the first and second stack structures.
8 . The semiconductor integrated circuit device of claim 1 , wherein a conductive plug is interposed between the at least one electrode of the first transistor and a source or a drain of the second transistor electrically connected to the at least one electrode of the first transistor.
9 . A semiconductor integrated circuit device comprising: a first deck including peripheral circuits integrated in a semiconductor substrate and a first insulation layer configured to electrically isolate the peripheral circuits from each other; a second deck arranged on the first deck, the second deck including memory cell arrays and a second insulation layer, each of the memory cell arrays including a plurality of memory cells controlled by the peripheral circuits, and the second insulation layer configured to electrically isolate the memory cell arrays from each other; an electric element provided to the first deck, the electric element corresponding to a part of the peripheral circuit; and a transistor including a channel layer formed in a contact hole passing through the first and second insulation layers to expose the electric element.
10 . The semiconductor integrated circuit device of claim 9 , wherein the transistor including the channel layer comprises: a vertical gate over a sidewall of the contact hole, the vertical gate spaced apart from the electric element exposed through the contact hole; a gate insulation layer over a surface of the vertical gate and the sidewall of the contact hole; a vertical channel layer over a surface of the gate insulation layer and a bottom surface of the contact hole; a gap-filling insulation layer configured to fill a space surrounded by the vertical channel layer; and a first junction region over the vertical channel layer and the gap-filling insulation layer, wherein a second junction region configured to generate a channel together with the first junction region comprises a part of the vertical channel layer on a bottom surface of the contact hole facing the first junction region.
11 . The semiconductor integrated circuit device of claim 10 , wherein the transistor including the channel layer further comprises a gate pad extended from the vertical gate along an upper surface of the second deck.
12 . The semiconductor integrated circuit device of claim 10 , wherein a conductive plug is interposed between the electric element and the vertical channel layer on the bottom surface of the contact hole.
13 . The semiconductor integrated circuit device of claim 10 , wherein at least one additional deck is interposed between the first deck and the second deck, the additional deck comprises an insulation layer configured to electrically isolate memory cell arrays from each other, and the contact hole is formed through the insulation layer of the additional deck.
14 . The semiconductor integrated circuit device of claim 9 , wherein the electric element comprises any one of a gate, a source and a drain of a transistor in the peripheral circuit, or any one of wirings electrically connected to the gate, the source and the drain of the transistor in the peripheral circuits.
15 . The semiconductor integrated circuit device of claim 9 , wherein the memory cell array comprises: a stack structure including a plurality of insulation layers and a plurality of cell gates alternately stacked; and a plurality of channel structures through the stack structure.
16 . A method of manufacturing a semiconductor integrated circuit device, the method comprising: forming an electric element on a semiconductor substrate; forming an insulating interlayer on the semiconductor substrate with the electric element; etching the insulating interlayer to form a first contact hole configured to expose the electric element; and forming a transistor having a vertical channel in the first contact hole, wherein forming the transistor having the vertical channel comprises: forming a vertical gate on a sidewall of the first contact hole; forming a gate insulating layer on a surface of the vertical gate and the sidewall of the contact hole; forming a vertical channel layer on a surface of the gate insulation layer and the electric element exposed through the first contact hole; and forming a junction region in an upper region of the vertical channel layer.
17 . The method of claim 16 , wherein forming the electric element comprises at least one of forming a gate on the semiconductor substrate, implanting impurities into the semiconductor substrate at both sides of the gate to form a source and a drain and forming a wiring connection connected to the gate, the source and the drain, wherein the electric element is at least one of the gate, the source, the drain and the wiring connection.
18 . The method of claim 16 , further comprising at least once repeatedly forming a stack type memory cell array on the semiconductor substrate with the electric element, wherein the insulating interlayer has a thickness greater than a height of the stack type memory cell arrays.
19 . The method of claim 16 , further comprising: simultaneously forming a first contact hole and a second contact hole in the insulating interlayer between forming the insulating interlayer and forming the transistor including the vertical channel; and selectively forming a conductive wiring in the second contact hole.
20 . The method of claim 16 , wherein forming the junction region comprises: forming a gap-filling insulation layer in a space surrounded by the vertical channel layer in the first contact hole; recessing the gap-filling insulation layer to define a region where the junction region is to be formed, the gap-filling insulation layer having a height lower than a height of the first contact hole; forming a semiconductor layer in the region, the semiconductor layer including a material substantially the same as a material of the vertical channel layer; and implanting impurities into the semiconductor layer to form the junction region.

Description

CROSS-REFERENCES TO RELATED APPLICATION The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2021-0179435, filed on Dec. 15, 2021, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. BACKGROUND 1. Technical Field Various embodiments generally relate to a semiconductor integrated circuit device and a method of manufacturing the semiconductor integrated circuit device, more particularly, to a semiconductor integrated circuit device relating to an integration degree, and a method of manufacturing the semiconductor integrated circuit device. 2. Related Art A multi-stack technology whereby three-dimensional stacked memory cell arrays are stacked has been proposed in response to integration degrees of memory devices greatly increasing. Further, in order to secure an area of the memory cell array, peripheral circuits may be arranged under the memory cell array, Thus, electrical connection paths between memory cells and the peripheral circuits may be changed from a horizontal structure to a vertical structure. SUMMARY According to an example of an embodiment, there may be provided a semiconductor integrated circuit device. The semiconductor integrated circuit device may include a semiconductor substrate, a first transistor, an insulation interlayer and a second transistor. The first transistor may be formed over the semiconductor to substrate. The first transistor may include a horizontal channel substantially parallel to a surface of the semiconductor substrate. The insulating interlayer may be formed over an upper surface of the semiconductor substrate. A contact hole may be formed through the insulating interlayer. The second transistor may include a channel is layer in the contact hole, Any one of a source and a drain of the second transistor may be electrically connected to any one of electrodes of the first transistor. According to an example of an embodiment, there may be provided a semiconductor integrated circuit device. The semiconductor integrated circuit device may include a first deck, a second deck, an electric element and a vertical channel transistor. The first deck may include peripheral circuits integrated in a semiconductor substrate, and a first insulation layer configured to electrically isolate the peripheral circuits from each other. The second deck may be positioned over the first deck. The second deck may include a plurality of memory cell arrays and a second insulation layer. Each of the memory cell arrays may include a plurality of memory cells controlled by the peripheral circuits. The second insulation layer may be configured to electrically isolate the memory cell arrays from each other. The electric element may be provided to the first deck. The electric element may correspond to a part of the peripheral circuit. The vertical channel transistor may be integrated in a contact hole passing through the first and second insulation layers to expose the electric element. According to an example of an embodiment, there may be provided a method of manufacturing a semiconductor integrated circuit device. In a method of the manufacturing the semiconductor integrated circuit device, an electric element may be formed on a semiconductor substrate. An insulating interlayer may be formed on the semiconductor substrate. The insulating interlayer may be etched to form a first contact hole configured to expose the electric element. A transistor including a vertical channel may be formed in the first contact hole. In an example of an embodiment, forming the transistor with the vertical channel may include forming a vertical gate at a sidewall of the first contact hole, forming a gate insulation layer a surface of the vertical gate and the sidewall of the first contact hole, forming a vertical channel layer on a surface of the gate insulation layer and the electric element exposed through the first contact hole, and forming a junction region on the vertical channel layer. BRIEF DESCRIPTION OF THE DRAWINGS The above and another aspects, features and advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a circuit diagram illustrating a semiconductor integrated circuit device in accordance with examples of embodiments; FIG. 2 is a cross-sectional view taken illustrating the semiconductor integrated circuit device in FIG. 1; FIG. 3 is a cross-section& view illustrating a semiconductor integrated circuit device in accordance with examples of embodiments; FIG. 4 is a cross-sectional view illustrating a semiconductor integrated circuit device in accordance with examples of embodiments; FIGS. 5 to 9 are cross-sectional views illustrating a method of manufacturing a semiconductor integrated circuit device in accordance with examples of embodiments; FIG. 10 is a plan view o