US-12621997-B2 - Semiconductor devices

Abstract

A semiconductor device includes a bit line structures on a substrate, extending in a first direction, and being spaced apart from each other in a second direction; channels contacting upper surfaces of the bit line structures and being spaced apart from each other in the first and second directions; upper gate structures extending in the second direction and surrounding the channels disposed in the second direction, the upper gate structures being spaced apart in the first direction; and a capacitor structure including first capacitor electrodes respectively on the channels; a dielectric layer on the first capacitor electrodes, the dielectric layer including a ferroelectric material or an anti-ferroelectric material; a second capacitor electrode layer on the dielectric layer; and capacitor plate electrodes on the second capacitor electrode layer, the capacitor plate electrodes each extending in the second direction and being spaced apart from each other in the first direction.

Inventors

• Kiseok LEE
• Jinwoo Han
• HanJin LIM

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20231117

Priority Date

20230424

Claims (20)

1. 1 . A semiconductor device, comprising: a substrate; bit line structures on the substrate, the bit line structures each extending in a first direction substantially parallel to an upper surface of the substrate and being spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction; channels contacting upper surfaces of the bit line structures and being spaced apart from each other in the first and second directions; upper gate structures each extending in the second direction and surrounding the channels disposed in the second direction, the upper gate structures being spaced apart from each other in the first direction; and a capacitor structure, the capacitor structure including: first capacitor electrodes respectively on the channels; a dielectric layer on the first capacitor electrodes, the dielectric layer including a ferroelectric material or an anti-ferroelectric material; a second capacitor electrode layer on the dielectric layer; and capacitor plate electrodes on the second capacitor electrode layer, the capacitor plate electrodes each extending in the second direction and being spaced apart from each other in the first direction.
2. 2 . The semiconductor device according to claim 1 , wherein each of the capacitor plate electrodes overlaps a corresponding one of the upper gate structures in a third direction substantially perpendicular to the upper surface of the substrate.
3. 3 . The semiconductor device according to claim 1 , wherein: each of the first capacitor electrodes and the second capacitor electrode layer includes a metal or a metal nitride, and each of the capacitor plate electrodes includes silicon-germanium doped with an impurity.
4. 4 . The semiconductor device according to claim 1 , wherein the upper gate structure includes: upper gate insulation patterns respectively on sidewalls of the channels, respectively; and an upper gate electrode extending in the second direction, the upper gate electrode contacting and surrounding outer sidewalls of the upper gate insulation patterns.
5. 5 . The semiconductor device according to claim 4 , wherein the upper gate electrode has an upper surface that is lower than an upper surface of the upper gate insulation patterns.
6. 6 . The semiconductor device according to claim 5 , further comprising an insulation pattern on the upper gate electrode, the insulation pattern having an upper surface that is substantially coplanar with the upper surface of the upper gate insulation patterns.
7. 7 . The semiconductor device according to claim 4 , further comprising: an insulating interlayer covering sidewalls and the upper surfaces of the bit line structures; and a spacer layer on the insulating interlayer, wherein: each of the channels extends through a corresponding one of the upper gate structures, the spacer layer, and an upper portion of the insulating interlayer and contacts an upper surface of a corresponding one of the bit line structures; and the upper gate structures are on the spacer layer.
8. 8 . The semiconductor device according to claim 7 , wherein the gate insulation patterns are connected to each other and contact an upper surface of the spacer layer.
9. 9 . The semiconductor device according to claim 1 , wherein each of the channels includes polysilicon or single crystalline silicon.
10. 10 . The semiconductor device according to claim 9 , further comprising an impurity region at an upper portion of each of the channels, the impurity region being doped with n-type impurities or p-type impurities.
11. 11 . The semiconductor device as claimed in claim 1 , wherein: the bit line structure includes a first bit line and a second bit line stacked in a third direction substantially perpendicular to the upper surface of the substrate, the first bit line includes a metal, and the second bit line includes polysilicon doped with impurities.
12. 12 . The semiconductor device according to claim 1 , further comprising transistors, each transistor including: a lower gate structure on the substrate; and impurity regions at upper portions of the substrate adjacent to the lower gate structure, wherein the transistors are electrically connected to the bit line structures, respectively.
13. 13 . A semiconductor device, comprising: a substrate; a lower circuit pattern on the substrate, the lower circuit pattern including a lower gate structure and a first impurity region; a bit line structure on the lower circuit pattern, the bit line structure being electrically connected to the lower circuit pattern; a channel contacting an upper surface of the bit line structure, the channel including a second impurity region at an upper portion thereof; an upper gate structure surrounding the channel, the upper gate structure being spaced apart from the bit line structure; and a capacitor structure, the capacitor structure including: a first capacitor electrode on the second impurity region; a dielectric layer on the first capacitor electrode, the dielectric layer including a ferroelectric material or an anti-ferroelectric material; a second capacitor electrode on the dielectric layer; and a capacitor plate electrode on the second capacitor electrode.
14. 14 . The semiconductor device according to claim 13 , wherein: the channel includes polysilicon, and the second impurity region includes n-type impurities or p-type impurities.
15. 15 . The semiconductor device according to claim 13 , wherein the upper gate structure includes: an upper gate insulation pattern on a sidewall of the channel; and an upper gate electrode contacting an outer sidewall of the upper gate insulation pattern.
16. 16 . The semiconductor device according to claim 15 , further comprising an insulation pattern on the upper gate electrode, wherein: the upper gate electrode has an upper surface that is lower than an upper surface of the upper gate insulation pattern, and the insulation pattern has an upper surface that is substantially coplanar with the upper surface of the upper gate insulation pattern.
17. 17 . A semiconductor device, comprising: a substrate; bit line structures on the substrate, the bit line structures each extending in a first direction substantially parallel to an upper surface of the substrate, and being spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction; an insulating interlayer on the substrate, the insulating interlayer covering sidewalls and upper surfaces of the bit line structures; a spacer layer on the insulating interlayer; upper gate structures on the spacer layer, the upper gate structures each extending in the second direction and being spaced apart from each other in the first direction; channels each extending through a corresponding one of the upper gate structures, the spacer layer, and an upper portion of the insulating interlayer and contacting an upper surface of a corresponding one of the bit line structures, the channels being spaced apart from each other in the first and second directions; and a capacitor structure, the capacitor structure including: first capacitor electrodes respectively on the channels; a dielectric layer on the first capacitor electrodes, the dielectric layer including a ferroelectric material or an anti-ferroelectric material; a second capacitor electrode layer on the dielectric layer; and capacitor plate electrodes on the second capacitor electrode layer, the capacitor plate electrodes each extending in the second direction and being spaced apart from each other in the first direction.
18. 18 . The semiconductor device according to claim 17 , wherein each of the capacitor plate electrodes overlaps a corresponding one of the upper gate structures in a third direction substantially perpendicular to the upper surface of the substrate.
19. 19 . The semiconductor device according to claim 18 , further comprising transistors, each transistor including: a lower gate structure on the substrate; and impurity regions at upper portions of the substrate adjacent to the lower gate structure, wherein the transistors are electrically connected to the bit line structures, respectively.
20. 20 . The semiconductor device according to claim 17 , wherein the upper gate structure includes: upper gate insulation patterns respectively on sidewalls of the channels; and an upper gate electrode extending in the second direction, the upper gate electrode contacting and surrounding outer sidewalls of the upper gate insulation patterns.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0053555 filed on Apr. 24, 2023, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety. 1. FIELD Embodiments relate to a semiconductor device. 2. DESCRIPTION OF THE RELATED ART A VCT DRAM device may include a bit line structure, a gate structure, a channel, and a capacitor structure. A dielectric layer included in the capacitor structure may include a paraelectric material, which has volatile characteristics. SUMMARY The embodiments may be realized by providing a semiconductor device including a substrate; bit line structures on the substrate, the bit line structures each extending in a first direction substantially parallel to an upper surface of the substrate and being spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction; channels contacting upper surfaces of the bit line structures and being spaced apart from each other in the first and second directions; upper gate structures each extending in the second direction and surrounding the channels disposed in the second direction, the upper gate structures being spaced apart from each other in the first direction; and a capacitor structure, the capacitor structure including first capacitor electrodes respectively on the channels; a dielectric layer on the first capacitor electrodes, the dielectric layer including a ferroelectric material or an anti-ferroelectric material; a second capacitor electrode layer on the dielectric layer; and capacitor plate electrodes on the second capacitor electrode layer, the capacitor plate electrodes each extending in the second direction and being spaced apart from each other in the first direction. The embodiments may be realized by providing a semiconductor device including a substrate; a lower circuit pattern on the substrate, the lower circuit pattern including a lower gate structure and a first impurity region; a bit line structure on the lower circuit pattern, the bit line structure being electrically connected to the lower circuit pattern; a channel contacting an upper surface of the bit line structure, the channel including a second impurity region at an upper portion thereof; an upper gate structure surrounding the channel, the upper gate structure being spaced apart from the bit line structure; and a capacitor structure, the capacitor structure including a first capacitor electrode on the second impurity region; a dielectric layer on the first capacitor electrode, the dielectric layer including a ferroelectric material or an anti-ferroelectric material; a second capacitor electrode on the dielectric layer; and a capacitor plate electrode on the second capacitor electrode. The embodiments may be realized by providing a semiconductor device including a substrate; bit line structures on the substrate, the bit line structures each extending in a first direction substantially parallel to an upper surface of the substrate, and being spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction; an insulating interlayer on the substrate, the insulating interlayer covering sidewalls and upper surfaces of the bit line structures; a spacer layer on the insulating interlayer; upper gate structures on the spacer layer, the upper gate structures each extending in the second direction and being spaced apart from each other in the first direction; channels each extending through a corresponding one of the upper gate structures, the spacer layer, and an upper portion of the insulating interlayer and contacting an upper surface of a corresponding one of the bit line structures, the channels being spaced apart from each other in the first and second directions; and a capacitor structure, the capacitor structure including first capacitor electrodes respectively on the channels; a dielectric layer on the first capacitor electrodes, the dielectric layer including a ferroelectric material or an anti-ferroelectric material; a second capacitor electrode layer on the dielectric layer; and capacitor plate electrodes on the second capacitor electrode layer, the capacitor plate electrodes each extending in the second direction and being spaced apart from each other in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS Features will be apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which: FIGS. 1 to 3 are a perspective view and cross-sectional views illustrating a semiconductor device in accordance with example embodiments. FIGS. 4 to 24 are perspective views and cross-sectional views of stages in a method of manufacturing a semiconductor device in accordance with example embodiments. FIG. 25 i