US-12621998-B2 - Method and structures pertaining to improved ferroelectric random-access memory (FeRAM)

Abstract

Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

Inventors

• Tzu-Yu Chen
• Kuo-Chi Tu
• Sheng-Hung SHIH
• Fu-Chen Chang

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260505

Application Date

20240627

Claims (20)

1. 1 . An integrated circuit, comprising: a semiconductor substrate; an interconnect structure disposed over an upper surface of the semiconductor substrate, the interconnect structure comprising: a bottommost metal layer, an inter-metal layer disposed over the bottommost metal layer, a top metal layer disposed over the inter-metal layer, and a bond pad layer disposed over the top metal layer, wherein the top metal layer has a thickness that is greater than a thickness of the bottommost metal layer; and a ferroelectric structure arranged over an upper surface of the semiconductor substrate and under the bottommost metal layer, wherein the ferroelectric structure includes an upper ferroelectric portion having a first width, and a lower ferroelectric portion having a second width, such that a ledge corresponds to a height where the upper ferroelectric portion meets the lower ferroelectric portion.
2. 2 . The integrated circuit of claim 1 , wherein the ledge is apart from an uppermost surface of the ferroelectric structure by a distance that is approximately 5% to approximately 30% of a total height of the ferroelectric structure.
3. 3 . The integrated circuit of claim 1 , wherein the ferroelectric structure is included in a ferroelectric capacitor structure, wherein the ferroelectric structure is sandwiched between a bottom electrode and a top electrode of the ferroelectric capacitor structure, further comprising: a dielectric sidewall spacer structure disposed about outer sidewalls of the top electrode; and a conductive residue disposed along outermost sidewalls of the dielectric sidewall spacer structure, along outermost sidewalls of the ferroelectric structure, and along outermost sidewalls of the bottom electrode.
4. 4 . The integrated circuit of claim 3 , further comprising: a hardmask over an upper surface of the top electrode.
5. 5 . The integrated circuit of claim 4 , further comprising: a first dielectric liner along outermost sidewalls of the dielectric sidewall spacer structure and over an upper surface of the hardmask.
6. 6 . The integrated circuit of claim 5 , wherein the first dielectric liner comprises silicon carbide.
7. 7 . The integrated circuit of claim 5 , further comprising: a second dielectric liner along outermost sidewalls of the first dielectric liner and over an upper surface of the first dielectric liner.
8. 8 . An integrated circuit, comprising: a semiconductor substrate; an interconnect structure disposed over an upper surface of the semiconductor substrate, the interconnect structure comprising: a bottommost metal layer, an inter-metal layer disposed over the bottommost metal layer, a top metal layer disposed over the inter-metal layer, and a bond pad layer disposed over the top metal layer, wherein the top metal layer has a width and a thickness that are greater than a width and a thickness, respectively, of the inter-metal layer; and a capacitor structure included in the interconnect structure and including a capacitor dielectric sandwiched between a bottom electrode and a top electrode, the capacitor dielectric comprising: strontium bismuth tantalite, lead zirconate titanate, hafnium zirconium oxide, or doped hafnium oxide; and a conductive residue disposed along outermost sidewalls of the capacitor dielectric.
9. 9 . The integrated circuit of claim 8 , further comprising: a dielectric sidewall spacer structure disposed about outer sidewalls of the top electrode; and a dielectric hardmask disposed over the top electrode and disposed within inner sidewalls of the dielectric sidewall spacer structure.
10. 10 . The integrated circuit of claim 9 , further comprising: a first liner along outermost sidewalls of the dielectric sidewall spacer structure and over an upper surface of the dielectric hardmask; a second liner along outermost sidewalls of the first liner and over an upper surface of the first liner, the second liner having a second composition that differs from a first composition of the first liner; and a via that extends through the dielectric hardmask, through the first liner, and through the second liner to make electrical contact with the top electrode.
11. 11 . The integrated circuit of claim 9 , wherein the conductive residue is disposed along outermost sidewalls of the dielectric sidewall spacer structure and along outermost sidewalls of the bottom electrode.
12. 12 . The integrated circuit of claim 11 , wherein the conductive residue includes a chemical species, and the capacitor structure includes the chemical species.
13. 13 . An integrated circuit, comprising: a semiconductor substrate; an interconnect structure disposed over an upper surface of the semiconductor substrate, the interconnect structure comprising: a bottommost metal layer, a plurality of inter-metal layers disposed at different heights over the bottommost metal layer, and a plurality of top metal layers disposed at different heights over the inter-metal layers, and a bond pad layer disposed over the plurality of top metal layers; wherein each of the plurality of top metal layers has a width and a thickness that is greater than a width and a thickness, respectively, of each of the plurality of inter-metal layers; and a ferroelectric structure comprising an upper ferroelectric portion having a first width, and a lower ferroelectric portion having a second width greater than the first width such that a ledge corresponds to a height where the upper ferroelectric portion meets the lower ferroelectric portion.
14. 14 . The integrated circuit of claim 13 , wherein the ferroelectric structure is included in a ferroelectric capacitor structure, wherein the ferroelectric structure is sandwiched between a bottom electrode structure and a top electrode structure of the ferroelectric capacitor structure, and further comprising: a dielectric sidewall spacer structure disposed on the ledge and covering outermost sidewalls of the top electrode structure.
15. 15 . The integrated circuit of claim 14 , further comprising: a conductive residue disposed along outermost sidewalls of the dielectric sidewall spacer structure, along outermost sidewalls of the ferroelectric structure, and along outermost sidewalls of the bottom electrode structure.
16. 16 . The integrated circuit of claim 14 , further comprising: a barrier layer along the outer sidewalls of a bottom portion of the bottom electrode structure and along a bottom surface of the bottom portion of the bottom electrode structure.
17. 17 . The integrated circuit of claim 13 , wherein the width of each of the plurality of top metal layers is greater than 0.1 micrometers and the thickness of each of the plurality of top metal layers is between 1500 angstroms and 10000 angstroms, and wherein the width of each of the plurality of inter-metal layers is greater than 50 nanometers and the thickness of each of the plurality of inter-metal layers is between 500 angstroms and 1500 angstroms.
18. 18 . The integrated circuit of claim 1 , the ferroelectric structure comprising: strontium bismuth tantalite, lead zirconate titanate, hafnium zirconium oxide, or doped hafnium oxide.
19. 19 . The integrated circuit of claim 1 , wherein the width of the top metal layer is greater than 0.1 micrometers and the thickness of the top metal layer is between 1500 angstroms and 10000 angstroms, and wherein the width of the inter-metal layer is greater than 50 nanometers and the thickness of the inter-metal layer is between 500 angstroms and 1500 angstroms.
20. 20 . The integrated circuit of claim 8 , wherein the capacitor dielectric comprises an upper portion having a first width, and a lower portion having a second width greater than the first width such that a ledge corresponds to a height where the upper portion meets the lower portion.

Description

REFERENCE TO RELATED APPLICATIONS This Application is a Continuation of U.S. application Ser. No. 18/336,093, filed on Jun. 16, 2023, which is a Continuation of U.S. application Ser. No. 17/376,531, filed on Jul. 15, 2021 (now U.S. Pat. No. 11,723,213, issued on Aug. 8, 2023), which is a Continuation-in-Part of U.S. application Ser. No. 16/452,965, filed on Jun. 26, 2019 (now U.S. Pat. No. 11,195,840, issued on Dec. 7, 2021), which claims the benefit of U.S. Provisional Application No. 62/738,604, filed on Sep. 28, 2018. The contents of the above-referenced Patent Applications are hereby incorporated by reference in their entirety. BACKGROUND Many modern day electronic devices include non-volatile memory. Non-volatile memory is electronic memory that is able to store data in the absence of power. A promising candidate for the next generation of non-volatile memory is ferroelectric random-access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A illustrates a cross-sectional view of some embodiments of an integrated circuit (IC) comprising a FeRAM cell. FIG. 1B illustrates a top view of some embodiments of an integrated circuit (IC) comprising a FeRAM cell consistent with FIG. 1A. FIGS. 1C-1D illustrate cross-sectional views of other embodiments of an IC comprising an FeRAM cell. FIGS. 2A-2I illustrate cross-sectional views of various embodiments of an IC comprising a memory area with one or more FeRAM cells, and a peripheral area including logic circuitry spaced apart from the memory area. FIGS. 3-13 illustrate a series of cross-sectional views of some embodiments of a method for forming an IC comprising a FeRAM cell. FIG. 14 illustrates some embodiments of a method in flow chart format for forming an IC comprising a FeRAM cell. DETAILED DESCRIPTION The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. A one-transistor one-capacitor (1T1C) memory cell is a type of memory comprising a capacitor and a transistor. The capacitor stores varying levels of charge which correspond to an individual bit of data stored in the capacitor, and the transistor facilitates access to the capacitor for read and write operations. The relatively simple structure of the 1T1C memory cell allows high memory density, which leads to high memory capacity and a low cost per bit. 1T1C memory cells are typically used with dynamic random-access memory (DRAM). However, DRAM is reaching performance limits, is volatile, has high power consumption, and depends upon complex refresh circuitry. Volatile memory is electronic memory that is unable to store data in the absence of power. A promising alternative to DRAM is ferroelectric random-access memory (FeRAM). In contrast with DRAM, FeRAM has lower power consumption, the potential for better performance, does not depend upon complex refresh circuitry, and is non-volatile. FeRAM memory cells include a transistor and a ferroelectric capacitor structure, which includes a ferroelectric structure sa