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US-12621999-B2 - Variable resistance memory device

US12621999B2US 12621999 B2US12621999 B2US 12621999B2US-12621999-B2

Abstract

A variable resistance memory device includes a support layer including an insulating material; a variable resistance layer on the support layer and including a variable resistance material; a capping layer between the support layer and the variable resistance layer and protecting the variable resistance layer; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; and a plurality of gate electrodes and a plurality of insulators alternately and repeatedly arranged on the gate insulating layer in a first direction parallel with the channel layer. The capping layer may maintain oxygen vacancies formed in the variable resistance layer.

Inventors

  • YOUNGJIN CHO
  • Seyun KIM
  • Yumin KIM
  • Doyoon KIM
  • Jinhong Kim
  • Soichiro MIZUSAKI

Assignees

  • SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date
20260505
Application Date
20211110
Priority Date
20210129

Claims (20)

  1. 1 . A variable resistance memory device comprising: a support layer including an insulating material; a variable resistance layer on the support layer and including a variable resistance material; a capping layer between the support layer and the variable resistance layer, the capping layer being configured to protect the variable resistance layer; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; and a plurality of gate electrodes and a plurality of insulators alternately and repeatedly arranged on the gate insulating layer in a first direction parallel with the channel layer, wherein the variable resistance layer includes a silicon oxide layer contacting the channel layer and the variable resistance material on the silicon oxide layer.
  2. 2 . The variable resistance memory device of claim 1 , wherein the capping layer includes a material configured to maintain an amount of oxygen vacancies formed in the variable resistance layer.
  3. 3 . The variable resistance memory device of claim 1 , wherein the capping layer includes a metal oxide that has an oxide formation energy having a greater absolute value than an absolute value of an oxide formation energy of the variable resistance material.
  4. 4 . The variable resistance memory device of claim 1 , wherein the variable resistance layer has a structure including a plurality of layers, and the capping layer includes an oxide that has an oxide formation energy having a greater absolute value than an absolute value of an oxide formation energy of a layer of the plurality of layers, and the layer contacts the capping layer.
  5. 5 . The variable resistance memory device of claim 1 , wherein a thickness of the variable resistance layer is equal to or less than about 100 nm.
  6. 6 . The variable resistance memory device of claim 5 , wherein a thickness of the capping layer is equal to or greater than about 2 nm.
  7. 7 . The variable resistance memory device of claim 1 , wherein a thickness of the capping layer is equal to or less than about 100 nm.
  8. 8 . The variable resistance memory device of claim 1 , wherein the variable resistance material is Ta 2 O 5 , and the capping layer includes any one of HfO 2 , Al 2 O 3 , ZrO 2 , MgO, CaO, SrO, BaO, La 2 O 3 , Nd 2 O 3 , Eu 2 O 3 , CeO 2 , Sm 2 O 3 , Gd 2 O 3 , Sc 2 O 3 , Lu 2 O 3 , and Y 2 O 3 .
  9. 9 . The variable resistance memory device of claim 1 , wherein the variable resistance material is TiO 2 , and the capping layer includes any one of HfO 2 , Al 2 O 3 , ZrO 2 , MgO, CaO, SrO, BaO, La 2 O 3 , Nd 2 O 3 , Eu 2 O 3 , CeO 2 , Sm 2 O 3 , Gd 2 O 3 , Sc 2 O 3 , Lu 2 O 3 , and Y 2 O 3 .
  10. 10 . The variable resistance memory device of claim 1 , wherein the variable resistance material is HfO 2 , and the capping layer includes any one of Al 2 O 3 , MgO, CaO, SrO, BaO, La 2 O 3 , Nd 2 O 3 , Eu 2 O 3 , CeO 2 , Sm 2 O 3 , Gd 2 O 3 , Sc 2 O 3 , Lu 2 O 3 , and Y 2 O 3 .
  11. 11 . The variable resistance memory device of claim 1 , wherein the variable resistance material is ZrO 2 , and the capping layer includes any one of MgO, CaO, SrO, BaO, La 2 O 3 , Nd 2 O 3 , Eu 2 O 3 , CeO 2 , Sm 2 O 3 , Gd 2 O 3 , Sc 2 O 3 , Lu 2 O 3 , and Y 2 O 3 .
  12. 12 . The variable resistance memory device of claim 1 , wherein the channel layer includes a polycrystalline silicon (poly-Si) material.
  13. 13 . The variable resistance memory device of claim 1 , wherein the support layer and the capping layer include a same material.
  14. 14 . The variable resistance memory device of claim 1 , wherein the support layer has a cylindrical shape and extends in the first direction, the variable resistance layer, the channel layer, and the gate insulating layer surround the support layer in a cylindrical shell form, sequentially in an order of the variable resistance layer, the channel layer, and the gate insulating layer, and the plurality of gate electrodes and the plurality of insulators alternately surround the gate insulating layer.
  15. 15 . The variable resistance memory device of claim 14 , wherein the capping layer includes an oxide that has an oxide formation energy having a greater absolute value than an absolute value of an oxide formation energy of the variable resistance material.
  16. 16 . The variable resistance memory device of claim 14 , wherein the variable resistance layer has a structure including a plurality of layers, and the capping layer includes an oxide that has an oxide formation energy having a greater absolute value than an absolute value of an oxide formation energy of a layer of the plurality of layers in the variable resistance layer, and the layer contacts the capping layer.
  17. 17 . The variable resistance memory device of claim 14 , wherein the support layer and the capping layer include a same material.
  18. 18 . The variable resistance memory device of claim 14 , further comprising: a drain structure and a source structure respectively contacting both ends of the channel layer and the variable resistance layer in the first direction; a bit line connected to the drain structure; a source line connected to the source structures; and a plurality of word lines respectively connected to the plurality of gate electrodes.
  19. 19 . An electronic device comprising: the variable resistance memory device of claim 1 .
  20. 20 . The variable resistance memory device of claim 1 , wherein the variable resistance layer directly contacts the capping layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0013469, filed on Jan. 29, 2021 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND 1. Field The present disclosure relates to a nonvolatile memory device using a variable resistance material. 2. Description of Related Art A nonvolatile memory device as a semiconductor memory device may not lose stored data even if the supply of power thereto is stopped. The nonvolatile memory device may include, for example, programmable read-only memory (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), a flash memory device, etc. Recently, in accordance with the trend of requirements for technologies having the characteristics of high integration, low power consumption, and random memory-cell access capability, next-generation semiconductor memory devices, such as magnetic random-access memory (MRAM) and phase-change random-access memory (PRAM), have been developed. These next-generation semiconductor memory devices may be implemented as resistance change devices, which have resistance values that change according to an applied current or voltage and which maintain the changed resistance values even if a current or voltage supply is stopped. In order to realize high integration and low power consumption, it may be desirable that the resistance change characteristics of a resistance change device occur at a low applied voltage. A wide range of resistance change may be desired. SUMMARY Provided is a variable resistance memory device having the improved variable resistance performance. Additional aspects will be set forth in part in the description that follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure. According to an embodiment, a variable resistance memory device may include a support layer including an insulating material; a variable resistance layer on the support layer and including a variable resistance material; a capping layer between the support layer and the variable resistance layer and being configured to protect the variable resistance layer; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; and a plurality of gate electrodes and a plurality of insulators alternately and repeatedly arranged on the gate insulating layer in a first direction that is parallel with the channel layer. In some embodiments, the capping layer may include a material configured to maintain an amount of oxygen vacancies formed in the variable resistance layer. In some embodiments, the capping layer may include an oxide that has an oxide formation energy having a greater absolute value than an absolute value of an oxide formation energy of the variable resistance material. In some embodiments, the variable resistance layer may have a structure including a plurality of layers, and the capping layer may include an oxide that has an oxide formation energy having a greater absolute value than an absolute value of an oxide formation energy of a layer of the plurality of layers. The layer may contact the capping layer. In some embodiments, a thickness of the variable resistance layer may be equal to or less than about 100 nm. In some embodiments, a thickness of the capping layer may be equal to or less than about 100 nm. In some embodiments, a thickness of the capping layer may be equal to or greater than about 2 nm. In some embodiments, the variable resistance material may be Ta2O5, and the capping layer may include any one of HfO2, Al2O3, ZrO2, MgO, CaO, SrO, BaO, La2O3, Nd2O3, Eu2O3, CeO2, Sm2O3, Gd2O3, Sc2O3, Lu2O3, and Y2O3. In some embodiments, the variable resistance material may be TiO2, and the capping layer may include any one of HfO2, Al2O3, ZrO2, MgO, CaO, SrO, BaO, La2O3, Nd2O3, Eu2O3, CeO2, Sm2O3, Gd2O3, Sc2O3, Lu2O3, and Y2O3. In some embodiments, the variable resistance material may be HfO2, and the capping layer may include any one of MgO, CaO, SrO, BaO, La2O3, Nd2O3, Eu2O3, CeO2, Sm2O3, Gd2O3, Sc2O3, Lu2O3, and Y2O3. In some embodiments, the variable resistance material may be ZrO2, and the capping layer may include any one of MgO, CaO, SrO, BaO, La2O3, Nd2O3, Eu2O3, CeO2, Sm2O3, Gd2O3, Sc2O3, Lu2O3, and Y2O3. In some embodiments, the channel layer may include a polycrystalline silicon (poly-Si) material. In some embodiments, the variable resistance layer may include a silicon oxide layer contacting the channel layer. The variable resistance material may be on the silicon oxide layer. In some embodiments, the support layer and the capping layer may include a same material. In some embodiments, the support layer may have a cylindrical shape extending in the first direction. The variable resistance layer, the channel layer, and the gate insulating layer may surr