US-12622000-B2 - Semiconductor package and method of manufacturing the semiconductor package

US12622000B2US 12622000 B2US12622000 B2US 12622000B2US-12622000-B2

Abstract

A semiconductor package includes a package substrate, a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip including a free end portion. Conductive wires respectively electrically connect chip pads of the first semiconductor chips to substrate pads of the package substrate. A plurality of first support structures each have a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip. The first support structures are inclined at an angle relative to the package substrate.

Inventors

Younghun CHEONG
Minchul Cho
Cheolsoo HAN

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20230208
Priority Date: 20220715

Claims (16)

1 . A semiconductor package, comprising: a package substrate; a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip comprising a free end portion; conductive wires respectively electrically connecting chip pads of the first semiconductor chips to substrate pads of the package substrate; and a plurality of first support structures, each having a first end attached to the upper surface of the package substrate and an opposite second end with an end attached to the free end portion of the uppermost semiconductor chip, wherein the first support structures are inclined at an angle relative to the package substrate.
2 . The semiconductor package of claim 1 , wherein at least one of the chip pads of the uppermost semiconductor chip is on an upper surface of the free end portion, and wherein the second ends of the first support structures supports are attached to a lower surface of the free end portion.
3 . The semiconductor package of claim 1 , wherein each of the first support structures comprises: a wire bonding portion on the package substrate; and a dummy wire having a first end joined to the wire bonding portion and an opposite second end contacting a lower surface of the free end portion.
4 . The semiconductor package of claim 1 , further comprising: at least one second semiconductor chip on the uppermost semiconductor chip of the plurality of first semiconductor chips, the at least one second semiconductor chip comprising a free end portion; and a plurality of second support structures, each having a first end attached to an upper surface of one of the plurality of first semiconductor chips and an opposite second end attached to the free end portion of the at least one second semiconductor chip.
5 . The semiconductor package of claim 1 , further comprising: a plurality of second semiconductor chips stacked on the first semiconductor chips in a stair-step configuration opposite to the stair-step configuration of the first semiconductor chips, the plurality of second semiconductor chips having an uppermost semiconductor chip at a second height from an upper surface one of the first semiconductor chips; and a plurality of third support structures, each having a first end attached to an upper surface of the one of the first plurality of semiconductor chips and an opposite second end attached to a free end portion of the uppermost semiconductor chip of the plurality of second semiconductor chips.
6 . The semiconductor package of claim 1 , wherein the angle is within a range of 0 degrees to 20 degrees.
7 . The semiconductor package of claim 6 , wherein the stair-step configuration of the plurality of first semiconductor chips extends in a first direction, and wherein each of the first support structures is angled toward the first direction.
8 . The semiconductor package of claim 6 , wherein the stair-step configuration of the plurality of first semiconductor chips extends in a first direction, and wherein each of the first support structures is angled toward a second direction opposite to the first direction.
9 . The semiconductor package of claim 1 , wherein the first support structures comprise at least one of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and titanium (Ti).
10 . The semiconductor package of claim 1 , wherein a diameter of each of the first support structures is within a range of 1.0 mm to 3.5 mm.
11 . A semiconductor package, comprising: a package substrate; a plurality of first semiconductor chips stacked on the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the package substrate, the uppermost semiconductor chip comprising bonding pads on an upper surface thereof, and the uppermost semiconductor chip comprising a free end portion; conductive wires electrically connecting the bonding pads to the package substrate; and a plurality of first support structures, each having an elongate linear shape from a first end attached to the upper surface of the package substrate to an opposite second end attached to the free end portion of the uppermost semiconductor chip, wherein the first support structures are inclined at an angle relative to the package substrate.
12 . The semiconductor package of claim 11 , wherein each of the first support structures comprises: a dummy pad on the package substrate; and a dummy wire having a first end joined to the dummy pad and an opposite second end contacting a lower surface of the free end portion.
13 . The semiconductor package of claim 11 , further comprising: at least one second semiconductor chip on the uppermost semiconductor chip of the plurality of first semiconductor chips, the at least one second semiconductor chip comprising a free end portion; and a plurality of second support structures, each having a first end attached to an upper surface of one of the plurality of first semiconductor chips and an opposite second end attached to the free end portion of the at least one second semiconductor chip.
14 . The semiconductor package of claim 13 , wherein the at least one second semiconductor chip comprises a plurality of second semiconductor chips stacked on the first semiconductor chips in a stair-step configuration opposite to the stair-step configuration of the first semiconductor chips, the plurality of second semiconductor chips having an uppermost semiconductor chip at a second height from an upper surface of one of the first semiconductor chips; and a plurality of third support structures, each having a first end attached to an upper surface of the one of the first plurality of semiconductor chips and an opposite second end attached to a free end portion of the uppermost semiconductor chip of the plurality of second semiconductor chips.
15 . The semiconductor package of claim 11 , wherein the first support structures comprise at least one of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and titanium (Ti).
16 . The semiconductor package of claim 11 , wherein a diameter of each of the first support structures is within a range of 1.0 mm to 3.5 mm.

Description

PRIORITY STATEMENT This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0087329, filed on Jul. 15, 2022 in the Korean Intellectual Property Office (KIPO), the entire contents of which are herein incorporated by reference. BACKGROUND 1. Field Example embodiments relate to semiconductor packages and methods of manufacturing semiconductor packages. More particularly, example embodiments relate to multi-chip packages in which semiconductor chips of different heights are disposed on a package substrate and methods of manufacturing the same. 2. Description of the Related Art In a multi-chip package (MCP), failures such as bouncing, wire bonding defects, and protrusion cracks may occur in an overhang portion of an uppermost semiconductor chip. Unfortunately, conventional methods for addressing these issues have certain limitations. For example, increasing a thickness of the uppermost semiconductor chip may cause an increase in an overall thickness of a semiconductor package. Adding spacer chips may consume space. Pausing manufacturing so that chip movements can dissipate may reduce productivity. SUMMARY Example embodiments provide a semiconductor package including a plurality of support structures for supporting an uppermost semiconductor chip. Example embodiments provide a method of manufacturing the semiconductor package. According to example embodiments, a semiconductor package includes a package substrate, a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip having a free end, conductive wires respectively electrically connecting chip pads of the first semiconductor chips to substrate pads of the package substrate, and a plurality of first support structures, each having a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip, wherein the first support structures are inclined at an angle relative to the package substrate. According to example embodiments, a semiconductor package includes a package substrate, a plurality of first semiconductor chips stacked on the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the package substrate, the uppermost semiconductor chip having bonding pads on an upper surface thereof, and the uppermost semiconductor chip having a free end portion, conductive wires electrically connecting the bonding pads to the package substrate, and a plurality of first support structures, each having a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip, wherein the first support structures are inclined at an angle relative to the package substrate. According to example embodiments, a method of manufacturing a semiconductor package includes forming support structures having a predetermined height in a vertical direction from an upper surface of a package substrate, stacking a plurality of semiconductor chips in a stair-step configuration up to a height equal to the predetermined height of the support structures, stacking an uppermost semiconductor chip on the support structures and the semiconductor chips, and connecting a conductive wire on the uppermost semiconductor chip, wherein forming the support structures includes, extending a conductive material drawn from a capillary to have a predetermined length equal to the predetermined height from the package substrate to contact the contact pad, forming a scratched portion in the conductive material in a state in which the conductive material is not attached to another contact pad, and erecting up the conductive material by moving the capillary in the vertical direction and cutting the scratched portion of the conductive material. According to example embodiments, a semiconductor package may include a package substrate, a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip having at a first height from the upper surface of the package substrate, the uppermost semiconductor chip having a free end portion, conductive wires respectively electrically connecting chip pads of the first semiconductor chips to substrate pads of the package substrate, and a plurality of first support structures, each having a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip, wherein the first support struc