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US-12622001-B2 - 3D semiconductor device, structure and methods with memory arrays and connectivity structures

US12622001B2US 12622001 B2US12622001 B2US 12622001B2US-12622001-B2

Abstract

A 3D semiconductor device including: a first level including a first single crystal layer and a memory control circuit including first transistors and control circuit connectivity provided by first, second, and third metal layers; a second level including second transistors (one which includes a metal gate) disposed atop the first level; third transistors disposed atop second transistors with a fourth metal layer disposed atop; a memory array including word-lines, the memory array includes at least four memory mini arrays, where each mini array includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second or third transistors; a connection path from the fourth metal to the third or second metal layer, which includes a via disposed through the second level, and where the memory control circuit includes at least one power down control circuit.

Inventors

  • Zvi Or-Bach
  • Jin-Woo Han
  • Brian Cronquist
  • Eli Lusky

Assignees

  • MONOLITHIC 3D INC.

Dates

Publication Date
20260505
Application Date
20250620

Claims (20)

  1. 1 . A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors; a first metal layer providing connectivity for said memory control circuit; a second metal layer providing connectivity for said memory control circuit; a third metal layer providing connectivity for said memory control circuit; a second level comprising a plurality of second transistors, said second level disposed atop said first level; a plurality of third transistors disposed atop said plurality of second transistors; a fourth metal layer disposed atop said plurality of third transistors; a memory array comprising word-lines, wherein said memory array comprises at least four memory mini arrays, wherein each of said memory mini arrays comprises at least four rows by four columns of memory cells, wherein at least one of said plurality of second transistors comprises a metal gate, and wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors; and a connection path from said fourth metal to said third metal layer or said second metal layer, wherein said connection path comprises a via disposed through said second level, and wherein said memory control circuit comprises at least one power down control circuit.
  2. 2 . The 3D semiconductor device according to claim 1 , wherein said memory control circuit is configured to control each of said four memory mini arrays independently.
  3. 3 . The 3D semiconductor device according to claim 1 , wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step.
  4. 4 . The 3D semiconductor device according to claim 1 , further comprising: a circuit which generates a differential signal.
  5. 5 . The 3D semiconductor device according to claim 1 , wherein said memory control circuit comprises at least one temperature sensor circuit.
  6. 6 . The 3D semiconductor device according to claim 1 , further comprising: an upper level disposed atop said fourth metal layer, wherein said upper level comprises a mono-crystalline silicon layer.
  7. 7 . The 3D semiconductor device according to claim 1 , further comprising: oxide to oxide bond regions and metal to metal bond regions.
  8. 8 . A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors; a first metal layer providing connectivity for said memory control circuit; a second metal layer providing connectivity for said memory control circuit; a third metal layer providing connectivity for said memory control circuit; a second level comprising a plurality of second transistors, said second level disposed atop said first level; a plurality of third transistors disposed atop said plurality of second transistors; a fourth metal layer disposed atop said plurality of third transistors; a memory array comprising word-lines, wherein said memory array comprises at least four memory mini arrays, wherein each of said memory mini arrays comprises at least four rows by four columns of memory cells, wherein at least one of said plurality of second transistors comprises a metal gate, and wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors; a connection path from said fourth metal to said third metal layer or said second metal layer, wherein said connection path comprises a via disposed through said second level; and a redundancy circuit.
  9. 9 . The 3D semiconductor device according to claim 8 , wherein said memory control circuit is configured to control each of said four memory mini arrays independently.
  10. 10 . The 3D semiconductor device according to claim 8 , wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step.
  11. 11 . The 3D semiconductor device according to claim 8 , further comprising: a circuit which generates a differential signal.
  12. 12 . The 3D semiconductor device according to claim 8 , wherein said memory control circuit comprises at least one temperature sensor circuit.
  13. 13 . The 3D semiconductor device according to claim 8 , further comprising: an upper level disposed atop said fourth metal layer, wherein said upper level comprises a mono-crystalline silicon layer.
  14. 14 . The 3D semiconductor device according to claim 8 , further comprising: oxide to oxide bond regions and metal to metal bond regions.
  15. 15 . A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer and a memory control circuit, said memory control circuit comprising a plurality of first transistors; a first metal layer providing connectivity for said memory control circuit; a second metal layer providing connectivity for said memory control circuit; a third metal layer providing connectivity for said memory control circuit; a second level comprising a plurality of second transistors, said second level disposed atop said first level; a plurality of third transistors disposed atop said plurality of second transistors; a fourth metal layer disposed atop said plurality of third transistors; a memory array comprising word-lines, wherein said memory array comprises at least four memory mini arrays, wherein each of said memory mini arrays comprises at least four rows by four columns of memory cells, wherein at least one of said plurality of second transistors comprises a metal gate, and wherein each of said memory cells comprises at least one of said plurality of second transistors or at least one of said plurality of third transistors; a connection path from said fourth metal to said third metal layer or said second metal layer, wherein said connection path comprises a via disposed through said second level; and a circuit which generates a differential signal.
  16. 16 . The 3D semiconductor device according to claim 15 , wherein said memory control circuit is configured to control each of said four memory mini arrays independently.
  17. 17 . The 3D semiconductor device according to claim 15 , wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step.
  18. 18 . The 3D semiconductor device according to claim 15 , wherein said memory control circuit comprises at least one temperature sensor circuit.
  19. 19 . The 3D semiconductor device according to claim 15 , further comprising: an upper level disposed atop said fourth metal layer, wherein said upper level comprises a mono-crystalline silicon layer.
  20. 20 . The 3D semiconductor device according to claim 15 , further comprising: oxide to oxide bond regions and metal to metal bond regions.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This application relates to the general field of Integrated Circuit (IC) devices and fabrication methods, and more particularly to multilayer or Three Dimensional Integrated Memory Circuit (3D-Memory) and Three Dimensional Integrated Logic Circuit (3D-Logic) devices and fabrication methods. 2. Discussion of Background Art Over the past 40 years, there has been a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling”; i.e., component sizes such as lateral and vertical dimensions within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today is that wires dominate the performance, functionality and power consumption of ICs. 3D stacking of semiconductor devices or chips is one avenue to tackle the wire issues. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), the transistors in ICs can be placed closer to each other. This reduces wire lengths and keeps wiring delay low, thus reducing power requirements and increasing performance. There are many techniques to construct 3D stacked integrated circuits or chips including: Through-silicon via (TSV) technology: Multiple layers of dice are constructed separately. Following this, they can be bonded to each other and connected to each other with through-silicon vias (TSVs).Monolithic 3D technology: With this approach, multiple layers of transistors and wires can be monolithically constructed. Some monolithic 3D and 3DIC approaches are described in U.S. Pat. Nos. 8,273,610, 8,298,875, 8,362,482, 8,378,715, 8,379,458, 8,450,804, 8,557,632, 8,574,929, 8,581,349, 8,642,416, 8,669,778, 8,674,470, 8,687,399, 8,742,476, 8,803,206, 8,836,073, 8,902,663, 8,994,404, 9,023,688, 9,029,173, 9,030,858, 9,117,749, 9,142,553, 9,219,005, 9,385,058, 9,406,670, 9,460,978, 9,509,313, 9,640,531, 9,691,760, 9,711,407, 9,721,927, 9,799,761, 9,871,034, 9,953,870, 9,953,994, 10,014,292, 10,014,318, 10,515,981, 10,892,016, 10,991,675, 11,121,121, 11,502,095, 10,892,016, and 11,270,988; and pending US. Patent Application Publications and applications, Ser. Nos. 14/642,724, 15/150,395, 15/173,686, 62/651,722; 62/681,249, 62/713,345, 62/770,751, 62/952,222, 62/824,288, 63/075,067, 63/091,307, 63/115,000, 63/220,443, 2021/0242189, 2020/0013791; and PCT Applications (and Publications): PCT/US2010/052093, PCT/US2011/042071 (WO2012/015550), PCT/US2016/52726 (WO2017053329), PCT/US2017/052359 (WO2018/071143), PCT/U S2018/0167 59 (WO2018144957), PCT/US2018/52332(WO 2019/0607 98), PCT/US2021/44110, and PCT/US22/44165. The entire contents of all of the foregoing patents, publications, and applications are incorporated herein by reference.Electro-Optics: There is also work done for integrated monolithic 3D including layers of different crystals, such as U.S. Pat. Nos. 8,283,215, 8,163,581, 8,753,913, 8,823,122, 9,197,804, 9,419,031, 9,941,319, 10,679,977, 10,943,934, 10,998,374, 11,063,071, and 11,133,344. The entire contents of all of the foregoing patents, publications, and applications are incorporated herein by reference. Additionally the 3D technology according to some embodiments of the invention may enable some very innovative IC devices alternatives with reduced development costs, novel and simpler process flows, increased yield, and other illustrative benefits. SUMMARY The invention relates to multilayer or Three Dimensional Integrated Circuit (3D IC) devices and fabrication methods. An important aspect of 3D ICs is technologies that allow layer transfer. These technologies include technologies that support reuse of the donor wafer, and technologies that support fabrication of active devices on the transferred layer to be transferred with it. In one aspect, a 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer, a third metal layer overlaying the second metal layer; a plurality of second transistors disposed atop the third metal layer, a plurality of third transistors disposed atop the plurality of second transistors; a fourth metal layer disposed atop the plurality of third transistors; a memory array including word-lines, where the memory array includes at least four memory mini arrays. where each of the memory mini arra