US-12622002-B2 - Semiconductor device including memory cell including thyristor and method of manufacturing the same

Abstract

A semiconductor device according to an embodiment includes a substrate, first and second pillar electrodes extending along a vertical direction substantially perpendicular to a surface of the substrate, and a plurality of memory cells disposed between the first and second pillar electrodes. Each of the plurality of memory cells includes first and second shared device layers that are disposed adjacent to the first and second pillar electrodes, respectively, and extend along the vertical direction, first and second base device layers disposed between the first and second shared device layers, and a control gate electrode disposed on one of the first and second base device layers. Both first and second base device layers are disposed on a plane over the substrate and substantially parallel to the surface of the substrate.

Inventors

• Bo Min Park
• Seung Wook Ryu

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260505

Application Date

20230720

Priority Date

20230215

Claims (17)

1. 1 . A semiconductor device comprising: a substrate; first and second pillar electrodes extending along a vertical direction substantially perpendicular to a surface of the substrate; and a plurality of memory cells disposed between the first and second pillar electrodes, wherein each of the plurality of memory cells includes: first and second shared device layers that are disposed adjacent to the first and second pillar electrodes, respectively, and extend along the vertical direction; first and second base device layers disposed between the first and second shared device layers, both first and second base device layers disposed on a plane over the substrate and substantially parallel to the surface of the substrate; and a control gate electrode disposed on one of the first and second base device layers.
2. 2 . The semiconductor device of claim 1 , wherein the plurality of memory cells are disposed along the vertical direction.
3. 3 . The semiconductor device of claim 1 , wherein the plurality of memory cells share the first and second shared device layers with each other.
4. 4 . The semiconductor device of claim 1 , wherein the first shared device layer is disposed to surround the first pillar electrode, and wherein the second shared device layer is disposed to surround the second pillar electrode.
5. 5 . The semiconductor device of claim 1 , wherein each of the plurality of memory cells includes an NPNP thyristor.
6. 6 . The semiconductor device of claim 1 , wherein the control gate electrode extends in a direction substantially parallel to the surface of the substrate.
7. 7 . The semiconductor device of claim 1 , wherein the first shared device layer contacts the first base device layer, wherein the second shared device layer contacts the second base device layer, and wherein the control gate electrode is disposed on the second base device layer.
8. 8 . The semiconductor device of claim 1 , wherein each of the first shared device layer and the second base device layer includes a p-type metal oxide semiconductor material, and wherein each of the second shared device layer and the first base device layer includes an n-type metal oxide semiconductor material.
9. 9 . The semiconductor device of claim 8 , wherein a concentration of a p-type carrier inside the first shared device layer is higher than a concentration of the p-type carrier inside the second base device layer, and wherein a concentration of an n-type carrier inside the second shared device layer is higher than a concentration of the n-type carrier inside the first base device layer.
10. 10 . The semiconductor device of claim 8 , wherein the p-type metal oxide semiconductor material includes at least one selected from the group consisting of SnO, CuO, Cu 2 O, NiO, CO 3 O 4 , and Cr 2 O 3 .
11. 11 . The semiconductor device of claim 8 , wherein the n-type metal oxide semiconductor material includes at least one selected from the group consisting of SnO 2 , In 2 O 3 , ZnO, indium zinc oxide (IZO), indium tin oxide (ITO), and indium gallium oxide (IGO).
12. 12 . The semiconductor device of claim 1 , wherein each of the first pillar electrode, the second pillar electrode, and the third control gate electrode includes at least one of a doped semiconductor material, metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, and conductive metal oxide.
13. 13 . A semiconductor device comprising: a substrate; first and second pillar electrodes extending along a vertical direction substantially perpendicular to a surface of the substrate; and a plurality of memory cells disposed between the first and second pillar electrodes and disposed along the vertical direction, wherein each of the plurality of memory cells includes: a first shared device layer including a p-type metal oxide semiconductor material and extending along the vertical direction; a first base device layer, including an n-type metal oxide semiconductor material, that is disposed over the substrate to contact the first shared device layer on a plane substantially parallel to the surface of the substrate; a second base device layer, including a p-type metal oxide semiconductor material, that is disposed to contact the first base device layer on the plane; a second shared device layer, including an n-type metal oxide semiconductor material, that extends in the vertical direction and contacts the second base device layer; and a control gate electrode disposed on the second base device layer.
14. 14 . The semiconductor device of claim 13 , wherein the first shared device layer is disposed to surround the first pillar electrode, and wherein the second shared device layer is disposed to surround the second pillar electrode.
15. 15 . The semiconductor device of claim 13 , wherein the plurality of memory cells share the first and second shared device layers with each other.
16. 16 . The semiconductor device of claim 13 , wherein the p-type metal oxide semiconductor material includes at least one selected from the group consisting of SnO, CuO, Cu 2 O, NiO, CO 3 O 4 , and Cr 2 O 3 , and wherein the p-type metal oxide semiconductor material includes at least one selected from the group consisting of SnO, CuO, Cu 2 O, NiO, CO 3 O 4 , and Cr 2 O 3 .
17. 17 . The semiconductor device of claim 13 , wherein a concentration of a p-type carrier inside the first shared device layer is higher than a concentration of the p-type carrier inside the second base device layer, and wherein a concentration of an n-type carrier inside the second shared device layer is higher than a concentration of the n-type carrier inside the first base device layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims priority under 35 U.S.C. § 119(a) to Korean Application No. 10-2023-0020360, filed in the Korean Intellectual Property Office on Feb. 15, 2023, which is incorporated herein by reference in its entirety. BACKGROUND 1. Technical Field The present disclosure generally relates to a semiconductor device and, more particularly, to a semiconductor device including a memory cell with a thyristor and a method of manufacturing the same. 2. Related Art With the trend of requiring high-density, high-speed, and low-power operation, the size of DRAM cell is continuously decreasing. As the size of the DRAM cell decreases, it becomes increasingly difficult to secure a cell capacitance required to identify a signal stored in the DRAM cell. Recently, research on a capacitor-less 1T DRAM device has been actively conducted as a move away from a memory device having the conventional one transistor-one capacitor (1T-1C) structure. As an example of the capacitor-less 1T DRAM device, a thyristor memory device (referred to as “thyristor”) has been proposed. In a thyristor, an electrical conduction state and an electrical blocking state implemented using turn-on and turn-off operations of the thyristor may be stored as different signal information. SUMMARY A semiconductor device according to an embodiment of the present disclosure may include a substrate, first and second pillar electrodes extending along a vertical direction substantially perpendicular to a surface of the substrate, and a plurality of memory cells disposed between the first and second pillar electrodes. Each of the plurality of memory cells may include first and second shared device layers that are disposed adjacent to the first and second pillar electrodes, respectively, and extend along the vertical direction, first and second base device layers disposed between the first and second shared device layers, both first and second base device layers disposed on a plane over the substrate and substantially parallel to the surface of the substrate, and a control gate electrode disposed on one of the first and second base device layers. A semiconductor device according to another embodiment of the present disclosure may include a substrate, first and second pillar electrodes extending along a vertical direction substantially perpendicular to a surface of the substrate, and a plurality of memory cells disposed between the first and second pillar electrodes and disposed along the vertical direction. Each of the plurality of memory cells may include a first shared device layer including a p-type metal oxide semiconductor material and extending along the vertical direction, a first base device layer disposed over the substrate to contact the first shared device layer on a plane substantially parallel to the surface of the substrate, a second base device layer disposed to contact the first base device layer on the plane, a second shared device layer that extends in the vertical direction and contacts the second base device layer, and a control gate electrode disposed on the second base device layer. The first base device layer includes an n-type metal oxide semiconductor material, the second base device layer includes a p-type metal oxide semiconductor material, and the second shared device layer includes an n-type metal oxide semiconductor material. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic circuit diagram illustrating a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a schematic view illustrating a memory cell of a semiconductor device according to an embodiment of the present disclosure. FIG. 3 is a schematic plan view illustrating a semiconductor device according to an embodiment of the present disclosure. FIG. 4 is a cross-sectional view of a semiconductor device of FIG. 3 taken along a line I-I′. FIG. 5 is a cross-sectional view of a semiconductor device of FIG. 4 taken along a line II-II′ and shown on an x-y plane. FIG. 6 is a cross-sectional view of a semiconductor device of FIG. 4 taken along a line III-III′ and shown on an x-y plane. FIGS. 7A to 20A are schematic plan views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. FIGS. 7B to 20B are cross-sectional views of structures shown in FIGS. 7A to 20A taken along a line A-A′ and shown on an x-y plane. FIG. 21 is a schematic plan view illustrating a semiconductor device according to another embodiment of the present disclosure. FIG. 22 is a cross-sectional view of a semiconductor device of FIG. 21 taken along a line IV-IV′. FIG. 23 is a cross-sectional view of a semiconductor device of FIG. 22 taken along a line VI-VI′ and shown on an x-y plane. FIG. 24 is a cross-sectional view of a semiconductor device of FIG. 22 taken along a line VII-VII′ and shown on an x-y plane. FIG. 25 is a cross-sectional view of a semiconductor device of