US-12622003-B2 - High density three-dimensional integrated capacitors

US12622003B2US 12622003 B2US12622003 B2US 12622003B2US-12622003-B2

Abstract

A component includes a substrate and electrically conductive layers formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The electrically conductive layers can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.

Inventors

Vage Oganesian
Belgacem Haba
Ilyas Mohammed
Piyush Savalia

Assignees

ADEIA SEMICONDUCTOR SOLUTIONS LLC

Dates

Publication Date: 20260505
Application Date: 20210510

Claims (9)

1 . A microelectronic element, comprising: a substrate having an upper planar surface, an opposite lower planar surface, and a side surface, wherein the upper planar surface comprises a circuit element and wherein the upper planar surface and the lower planar surface are perpendicular to the side surface; a first dielectric layer at least partially disposed in the substrate between the upper planar surface and the lower planar surface, the first dielectric layer comprising an undulating shape that has a first side and an opposite second side, wherein the undulating shape extends downwardly with respect to the upper planar surface and extends upwardly with respect to the lower planar surface when viewed from a perspective of the side surface; a first electrically conductive layer disposed on the first side of the first dielectric layer, wherein the first electrically conductive layer conforms to the undulating shape of the first dielectric layer; a second electrically conductive layer and a third electrically conductive layer disposed on the second side of the first dielectric layer, wherein the second and third electrically conductive layers conform to the undulating shape of the first dielectric layer; a second dielectric layer disposed between the second electrically conductive layer and the third electrically conductive layer; and a plurality of first electrodes electrically connected to the first electrically conductive layer, a second electrode electrically connected to the second electrically conductive layer, and a third electrode electrically connected to the third electrically conductive layer.
2 . The microelectronic element as claimed in claim 1 , wherein undulating portions of the first dielectric layer extend downwardly from the upper planar surface of the substrate to locations proximate to the lower planar surface.
3 . The microelectronic element as claimed in claim 1 , wherein the substrate is at a ground potential.
4 . The microelectronic element as claimed in claim 1 , wherein the substrate comprises silicon.
5 . The microelectronic element as claimed in claim 1 , wherein the second electrode is connected to an outer portion of the second electrically conductive layer; and the third electrode is connected to an outer portion of the third electrically conductive layer.
6 . The microelectronic element as claimed in claim 5 , wherein: the first electrically conductive layer, the second electrically conductive layer, the third electrically conductive layer, the first dielectric layer, and the second dielectric layer are disposed in one or more openings formed in the substrate; and the plurality of first electrodes are connected to corresponding locations on the first electrically conductive layer that are radially inward from connection locations of the second and third electrodes to the second and third electrically conductive layers.
7 . The microelectronic element as claimed in claim 1 , wherein when the microelectronic element is in use, the plurality of first electrodes and the third electrode are connected with a first electric potential and the second electrode is connected with a second electric potential.
8 . The microelectronic element as claimed in claim 1 , wherein the undulating shape comprises a peak and a trough, and wherein the peak is closer to the upper planar surface than the trough.
9 . The microelectronic element as claimed in claim 1 , wherein the circuit element is disposed at and below the upper planar surface.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 16/219,225, filed on Dec. 13, 2018, which is a divisional of U.S. patent application Ser. No. 15/198,524, filed on Jun. 30, 2016, now U.S. Pat. No. 10,157,978, which is a divisional of U.S. patent application Ser. No. 13/954,455, filed on Jul. 30, 2013, now U.S. Pat. No. 9,431,475, which is a divisional of U.S. patent application Ser. No. 12/964,049, filed on Dec. 9, 2010, now U.S. Pat. No. 8,502,340, the disclosures of which are incorporated herein by reference. BACKGROUND OF THE INVENTION The present invention relates to capacitors in semiconductor chips or particular types of substrates, e.g., semiconductor, glass, ceramic, or other relatively low CTE materials and methods of making such capacitors, and to components useful in such capacitors. Capacitors are commonly used for noise suppression, either in signal lines or in power lines. In power lines, noise suppression can be accomplished by mounting many capacitors along the power line to reduce the impedance level. Such capacitor mounting can increase the size and cost of the system, because the cost of mounting the capacitors can be higher than the cost of the capacitors. Capacitors can be provided on semiconductor chips having active circuit elements, i.e., “active chips” or can be provided on passive chips containing passive circuit elements such as capacitors, inductors, resistors, etc., for mounting to active chips. Conventional capacitors in silicon can be of two general types. A first type is used to store charge for each bit in a DRAM chip. A second type is capacitors on passive chips, where the primary focus has been on planar capacitors with very thin dielectric materials having a very high dielectric constant, in a single or multi-layer format. Both types of conventional capacitors can have limitations when applied to decoupling capacitor applications. The first type of capacitor may not be well suited for high capacitance applications, because that type is typically meant for usage at bit level and therefore is purposely designed to have a very small size. The first type typically lacks features needed to store or supply sufficient current as a decoupling capacitor. The second type of capacitor may have a low capacitance density and a low quality factor (efficiency). Further improvements would be desirable in the design of capacitors in microelectronic chips, semiconductor substrates, or other substrates having relatively low CTE such as glass or ceramic material. BRIEF SUMMARY OF THE INVENTION In accordance with an aspect of the invention, a component having electrodes for electrical interconnection with a circuit component or microelectronic element can include a substrate and a first capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a first surface, a second surface opposite the first surface, and a first opening extending downwardly from the first surface. The first capacitor can include at least first and second pairs of electrically conductive plates connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the first opening. Each of the plates can be separated from at least one adjacent plate by a dielectric layer. The first capacitor can include first and second electrodes. The first electrode can be exposed at the first surface and can be coupled to the first pair of plates. The second electrode can be exposed at one of the first and second surfaces and can be coupled to the second pair of plates. In a particular embodiment, each dielectric layer separating each of the plates from the at least one adjacent plate can be a dielectric layer having a dielectric constant k of at least 3. In one embodiment, a portion of the first opening that is not occupied by the first and second pairs of plates and the dielectric layers can be filled with a dielectric material. In an exemplary embodiment, the substrate can consist essentially of one material selected from the group consisting of: semiconductor, glass, and ceramic. In a particular embodiment, the first capacitor can have a capacitance of at least 1 picoFarad. In one embodiment, the first opening can have a width in a direction along the first surface of at least 5 microns. In an exemplary embodiment, the first opening can have a depth in a direction perpendicular to the first surface of at least 10 microns. In one embodiment, the first opening can have a frustoconical shape, the inner surface of the first opening extending at an angle of less than 80 degrees relative to the substrate first surface. In a particular embodiment, the first and second electrodes can be connected to the first and second pairs of plates at respective first and second locations, the