US-12622004-B2 - Semiconductor trench capacitor structure and manufacturing method thereof

Abstract

A semiconductor trench capacitor structure is provided. The semiconductor trench capacitor comprises a semiconductor substrate; a trench capacitor overlying the semiconductor substrate, wherein the trench capacitor comprises a plurality of trench electrodes and a plurality of capacitor dielectric layers that are alternatingly stacked over the semiconductor substrate and defines a plurality of trench segments and a plurality of pillar segments, wherein the trench electrodes and the capacitor dielectric layers are recessed into the semiconductor substrate at the trench segments, and wherein the trench segments are separated from each other by the pillar segments; and a protection dielectric layer disposed between the semiconductor substrate and the trench capacitor, wherein the protection dielectric layer has a thickness greater than thicknesses of the trench electrodes.

Inventors

• Fu-Chiang KUO

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Dates

Publication Date

20260505

Application Date

20240722

Claims (20)

1. 1 . A semiconductor structure, comprising: a semiconductor substrate; a metal-insulator-metal (MIM) trench capacitor on the semiconductor substrate and comprising a plurality of capacitor segments extending into the semiconductor substrate and separated from each other by pillar segments, wherein each pillar segment has a T-shape or a trapezoid shape, and has two sharp corners at a top portion, and two sidewalls beneath the two sharp corners and perpendicular to the semiconductor substrate; and a protection dielectric layer disposed over the two sharp corners of the pillar segments, so that the sidewalls of the pillar segments are in contact with a metal layer of the MIM trench capacitor.
2. 2 . The semiconductor structure of claim 1 , wherein the protection dielectric layer is a discontinuous protection dielectric layer.
3. 3 . The semiconductor structure of claim 1 , wherein the thickness of the protection dielectric layer is non-uniform.
4. 4 . The semiconductor structure of claim 3 , wherein the thickest thickness of the protection dielectric layer is about twice larger the thinnest thickness of the protection dielectric layer.
5. 5 . The semiconductor structure of claim 1 , wherein the protection dielectric layer completely overlies the two sharp corners of the pillar segments.
6. 6 . The semiconductor structure of claim 1 , wherein the protection dielectric layer is disposed discontinuously and at least covers the two sharp corners of the pillar segments.
7. 7 . The semiconductor structure of claim 1 , wherein each capacitor segment comprises an alternative stack of trench electrode layers and capacitor dielectric layers.
8. 8 . The semiconductor structure of claim 7 , wherein the protection dielectric layer has a thickness greater than a half of a thinnest thickness of each of the trench electrode layers.
9. 9 . The semiconductor structure of claim 7 , wherein the lowest trench electrode layer is in direct contact with the semiconductor substrate.
10. 10 . The semiconductor structure of claim 7 , wherein the lowest trench electrode layer is in direct contact with the sidewalls of the pillar segments of the MIM trench capacitor.
11. 11 . The semiconductor structure of claim 7 , wherein lowest trench electrode layer is in direct contact with top surfaces of the pillar segments of the MIM trench capacitor.
12. 12 . A semiconductor structure, comprising: a semiconductor substrate defining a trench, the trench including a top portion having a top width and a bottom portion having a bottom width, wherein the top width is less than the bottom width such that the semiconductor substrate comprises two sharp corners at a top portion thereof; a discontinuous protection dielectric layer completely overlying the two sharp corners of the semiconductor substrate; and a trench capacitor disposed over the semiconductor substrate and filling the trench, wherein the trench capacitor comprises: a first trench electrode layer overlying the semiconductor substrate and lining the trench; a capacitor dielectric layer overlying the first trench electrode layer and lining the trench over the first trench electrode layer; and a second trench electrode layer overlying the capacitor dielectric layer and filling the trench over the capacitor dielectric layer, wherein the protection dielectric layer has a thinnest thickness greater than a thinnest thickness of the first trench electrode layer or the second trench electrode layer.
13. 13 . The semiconductor structure of claim 12 , wherein the protection dielectric layer partially overlies the semiconductor substrate and the trench.
14. 14 . The semiconductor structure of claim 12 , wherein the first trench electrode layer is in direct contact with the semiconductor substrate.
15. 15 . The semiconductor structure of claim 12 , wherein the first trench electrode layer is in direct contact with a bottom surface and two sidewall surfaces of the trench.
16. 16 . The semiconductor structure of claim 12 , wherein the thickness of the protection dielectric layer is non-uniform.
17. 17 . The semiconductor structure of claim 16 , wherein the thickest thickness of the protection dielectric layer is about twice larger the thinnest thickness of the protection dielectric layer.
18. 18 . A method of forming a semiconductor device, the method comprising: providing a semiconductor substrate; performing an etch into the semiconductor substrate to form a trench, wherein the trench includes a top portion having a top width and a bottom portion having a bottom width, wherein the top width is less than the bottom width such that the semiconductor substrate comprises two sharp corners at a top portion thereof; forming a discontinuous protection dielectric layer completely overlying the two sharp corners of the semiconductor substrate; and forming a layer stack including at least two trench electrode layers interlaced with a capacitor dielectric layer over the semiconductor substrate and filling the trench; wherein the protection dielectric layer has a thickness greater than a half of a thinnest thicknesses of the at least two trench electrode layers.
19. 19 . The method of claim 18 , wherein the thickness of the protection dielectric layer is non-uniform, and a thinnest thickness of the protection dielectric layer is twice greater than the thinnest thickness of the at least two trench electrode layers.
20. 20 . The method of claim 18 , wherein the lower trench electrode layer is in direct contact with a bottom surface and two sidewall surfaces of the trench.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a continuation application of U.S. non-provisional application Ser. No. 18/327,869 filed on Jun. 1, 2023, which is a continuation application and claims the benefit of U.S. non-provisional application Ser. No. 17/461,734 filed on Aug. 30, 2021, now U.S. Pat. No. 11,817,510 B2; the disclosure of which are hereby incorporated by reference in its entirety. BACKGROUND Electronic equipment involving semiconductor devices are essential for many modern applications. Technological advances in materials and design have produced generations of semiconductor devices where each generation has smaller and more complex circuits than the previous generation. In the course of advancement and innovation, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component that can be created using a fabrication process) has decreased. Such advances have increased the complexity of processing and manufacturing semiconductor devices. Trench capacitors are commonly embedded in integrated passive devices and used in place of ceramic capacitors to reduce the size of mobile devices, reduce the cost of mobile devices, increase the functionality of mobile devices, or any combination of the foregoing. Trench capacitors are usually designed to possess a high aspect ratio in order to achieve a high-density layout. To provide improved characteristics and performance of the trench capacitors, metal-insulator-metal (MIM) capacitor designs comprising a plurality of metal layers and dielectric layers in an interleaved pattern have recently been introduced. When the layers of the MIM capacitors are formed within a recess having a high aspect ratio, the layers may be very thin and the distance between the layers may be short. Accordingly, there may be a greatly increased risk of device cracking due to at least uneven stress and the decreased distance between the layers. Therefore, an improved structure and manufacturing method of trench capacitors are desired. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying Figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a schematic view of a semiconductor trench capacitor structure according to various aspects of a comparative embodiment of the present disclosure. FIG. 2A, FIG. 2B, FIG. 3A, FIG. 3B, FIG. 3C, FIG. 4, FIG. 5, FIG. 6, and FIG. 7 are schematic views of manufacturing a semiconductor trench capacitor structure according to some embodiments of the present disclosure. FIG. 8 is a flow diagram of a method of manufacturing a semiconductor trench capacitor according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE DISCLOSURE The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the Figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the Figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer, or section from another. T