US-12622005-B2 - Integration scheme for fabricating high precision, low capacitor with unlanded via

Abstract

Semiconductor devices including a capacitor and methods of fabricating the semiconductor devices are disclosed. A method of fabricating a semiconductor device including a capacitor includes forming an underlayer structure including a substrate onto which metal is patterned within a first dielectric material, wherein the patterned metal forms a first metal surface of the capacitor; forming a middle layer of a second dielectric material above the underlayer structure; forming an upper layer of a third dielectric material above the middle layer; etching a supervia though the upper layer and into the middle layer, wherein the supervia hangs in the second dielectric material of the middle layer above the patterned metal forming the first metal surface of the capacitor; and performing barrier deposition and metal electroplating in the supervia, wherein the supervia forms a second metal surface of the capacitor above the first metal surface.

Inventors

• Sunil Kumar Singh
• Sivashankar Sivasubramanian

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20230130

Claims (16)

1. 1 . A method of fabricating a semiconductor device including a capacitor, the method comprising: forming an underlayer structure including a substrate onto which patterned metal is formed within a first dielectric material of the substrate, wherein the patterned metal forms a first metal surface of the capacitor; forming a middle layer of a second dielectric material above the underlayer structure; forming an upper layer of a third dielectric material above the middle layer; etching a supervia through the upper layer and into the middle layer, wherein the supervia is disposed in the second dielectric material of the middle layer above the patterned metal forming the first metal surface of the capacitor; and performing barrier deposition and metal electroplating in the supervia, wherein a metal on the supervia forms a second metal surface of the capacitor above the first metal surface.
2. 2 . The method of claim 1 , further comprising performing patterning and metallization on at least one of the middle layer or the upper layer.
3. 3 . The method of claim 1 , further comprising forming an etch stop layer on top of at least one of the underlayer structure or the middle layer.
4. 4 . The method of claim 1 , further comprising performing post-chemical mechanical polishing (CMP) capping on the upper layer before etching the supervia.
5. 5 . The method of claim 4 , further comprising performing supervia patterning on the post-CMP cap, wherein the supervia is etched according to the supervia patterning.
6. 6 . The method of claim 1 , further comprising forming a capping layer onto the upper layer after performing barrier deposition and metal electroplating in the supervia.
7. 7 . The method of claim 1 , wherein the first dielectric material, the second dielectric material, and the third dielectric material include a same dielectric material.
8. 8 . A method of fabricating a semiconductor device including a capacitor, the method comprising: forming an underlayer structure including a substrate onto which patterned metal is formed within a first dielectric material of the substrate, wherein the patterned metal forms a first metal surface of the capacitor; forming a middle layer of a second dielectric material above the underlayer structure; forming an upper layer of a third dielectric material above the middle layer; forming an unlanded via through the upper layer and into the middle layer, wherein the unlanded via is disposed in the second dielectric material of the middle layer above the patterned metal forming the first metal surface of the capacitor; and performing barrier deposition and metal electroplating on the upper layer, wherein a metal on the unlanded via forms a second metal surface of the capacitor above the first metal surface.
9. 9 . The method of claim 8 , further comprising performing patterning and metallization on the middle layer.
10. 10 . The method of claim 8 , further comprising forming an etch stop layer on top of at least one of the underlayer structure or the middle layer.
11. 11 . The method of claim 8 , further comprising forming a patterning film layer on the upper layer before forming an unlanded via.
12. 12 . The method of claim 11 , wherein the patterning film layer includes at least one of a first dielectric hard mask layer, a metal hard mask (MHM) layer, or a second dielectric hard mask layer.
13. 13 . The method of claim 11 , further comprising creating open areas of the patterning film layer by performing trench patterning.
14. 14 . The method of claim 13 , wherein forming the unlanded via comprises: performing via patterning and via etching on the opened areas; and performing final etching and cleaning on the patterned and etched via.
15. 15 . The method of claim 8 , further comprising forming a capping layer onto the upper layer after performing barrier deposition and metal electroplating on the upper layer.
16. 16 . The method of claim 8 , wherein the first dielectric material, the second dielectric material, and the third dielectric material include a same dielectric material.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 63/430,458, which was filed in the U.S. Patent and Trademark Office on Dec. 6, 2022, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD The disclosure generally relates to fabrication methods and resulting structures for semiconductor devices. More particularly, the subject matter disclosed herein relates to improvements to a capacitor structure for integrated circuit (IC) structure formation, and related methods to form the capacitor structure. BACKGROUND ICs generally become more complex and dense with each technology generation. With continued efforts toward reduction of feature size, use of multiple-patterning and other advanced lithography techniques have been on the rise. Generally, integrated circuits (ICs) include semiconductor devices formed as a configuration of circuits on a semiconductor substrate. A complex network of signal paths are routed to connect circuit elements distributed on the substrate. Efficient routing of these signals across the device normally requires formation of multilevel or multilayered conductive networks, which can be formed using schemes, such as, e.g., single or dual damascene wiring structures. Capacitor structures in an IC conventionally include two metal plates with an insulator between the plates. In such a configuration, the plates occupy at least a minimum surface area to achieve desired capacitances. A conventional approach for integrating capacitors into an integrated circuit is to form transverse metal lines, or “fingers,” extending outward from a larger wire interdigitating the transverse metal lines with similar metal lines of a nearby wire. However, such a configuration may impose limits on manufacturability and capacitance ranges as devices continue to decrease in size. These limits on a size of a capacitor may be problematic when a product specification requires a low capacitor, e.g., a capacitor with less than 0.5 femtofarads (fF). Previous approaches for providing low capacitance have included increasing a space between alternating horizontal electrodes in order to reduce capacitance density or serially connecting larger capacitors together in order to reduce effective capacitance between two nodes. However, these types of approaches have produced capacitors that are still too large and/or lack the desired precision for certain applications. SUMMARY Accordingly, an aspect of the disclosure is to provide a small, low metal-oxide-metal (MOM) capacitor, e.g., below 0.5 fF, with high precision and effective mismatch. Another aspect of the disclosure is to provide a customized design for an MOM capacitor. Another aspect of the disclosure is to provide an MOM capacitor utilizing a supervia structure for improved process control. Another aspect of the disclosure is to provide an MOM capacitor utilizing an unlanded via structure for simplified masking. In accordance with an aspect of the disclosure, a method is provided for fabricating a semiconductor device including a capacitor. The method includes forming an underlayer structure including a substrate onto which metal is patterned within a first dielectric material, wherein the patterned metal forms a first metal surface of the capacitor; forming a middle layer of a second dielectric material above the underlayer structure; forming an upper layer of a third dielectric material above the middle layer; etching a supervia though the upper layer and into the middle layer, wherein the supervia hangs in the second dielectric material of the middle layer above the patterned metal forming the first metal surface of the capacitor; and performing barrier deposition and metal electroplating in the supervia, wherein the supervia forms a second metal surface of the capacitor above the first metal surface. In accordance with another aspect of the disclosure, a method is provided for fabricating a semiconductor device including a capacitor. The method includes forming an underlayer structure including a substrate onto which metal is patterned within a first dielectric material, wherein the patterned metal forms a first metal surface of the capacitor; forming a middle layer of a second dielectric material above the underlayer structure; forming an upper layer of a third dielectric material above the middle layer; forming an unlanded via through the upper layer and into the middle layer, wherein the unlanded via hangs in the second dielectric material of the middle layer above the patterned metal forming the first metal surface of the capacitor; and performing barrier deposition and metal electroplating on the upper layer, wherein the unlanded via forms a second metal surface of the capacitor above the first metal surface. In accordance with another aspect of the disclosure, a semiconductor device including a capacitor is provided. The semiconductor de