US-12622006-B2 - Semiconductor device

US12622006B2US 12622006 B2US12622006 B2US 12622006B2US-12622006-B2

Abstract

A semiconductor device includes a semiconductor body having first and second surfaces opposite to each other. The semiconductor body includes a first well region having a first conductivity type, second and third well regions spaced apart from each other in a first direction with the first well region interposed therebetween and having a second conductivity type, first doped regions spaced apart from each other in a second direction intersecting the first direction in the first well region, a second doped region, which is adjacent to the second well region and has the second conductivity type, and a third doped region, which is adjacent to the third well region and has the second conductivity type. The second surface of the semiconductor body includes bottom surfaces of the first to third well regions, the plurality of first doped regions, the second doped region, and the third doped region.

Inventors

Sungil Park
Jae Hyun Park

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20230324
Priority Date: 20220407

Claims (14)

1 . A semiconductor device comprising: a semiconductor body having a first surface and a second surface, which are opposite to each other, wherein the semiconductor body comprises: a first well region having a first conductivity type; a second well region and a third well region, which are spaced apart from each other in a first direction with the first well region interposed therebetween and have a second conductivity type different from the first conductivity type; a plurality of first doped regions spaced apart from each other in a second direction intersecting the first direction in the first well region, the plurality of first doped regions having the first conductivity type, wherein a concentration of dopants having the first conductivity type in each of the plurality of first doped regions is greater than a concentration of dopants having the first conductivity type in the first well region; a second doped region, which is adjacent to the second well region and has the second conductivity type; and a third doped region, which is adjacent to the third well region and has the second conductivity type, wherein the second well region is disposed between the first well region and the second doped region, and the third well region is disposed between the first well region and the third doped region, and wherein the second surface of the semiconductor body comprises bottom surfaces of the first to third well regions, the plurality of first doped regions, the second doped region, and the third doped region.
2 . The semiconductor device of claim 1 , wherein a concentration of dopants having the second conductivity type in the second doped region is greater than a concentration of dopants having the second conductivity type in the second well region.
3 . The semiconductor device of claim 2 , wherein a concentration of dopants having the second conductivity type in the third doped region is greater than a concentration of dopants having the second conductivity type in the third well region.
4 . The semiconductor device of claim 1 , wherein each of the plurality of first doped regions has a bar shape extending in the first direction, and wherein a length, in the first direction, of each of the plurality of first doped regions is greater than a width, in the second direction, of each of the plurality of first doped regions.
5 . The semiconductor device of claim 4 , further comprising: a plurality of first contacts spaced apart from each other in the first direction on each of the plurality of first doped regions, wherein respective ones of the plurality of first contacts are electrically connected to corresponding ones of the plurality of first doped regions.
6 . The semiconductor device of claim 5 , further comprising: a plurality of first doped patterns penetrating the plurality of first doped regions, respectively, wherein respective ones of the plurality of first doped patterns are spaced apart from each other in the first direction and are electrically connected to corresponding ones of the plurality of first contacts.
7 . The semiconductor device of claim 6 , wherein the plurality of first doped patterns have the first conductivity type, and wherein a concentration of dopants having the first conductivity type in each of the plurality of first doped patterns is equal to or greater than the concentration of the dopants having the first conductivity type in each of the plurality of first doped regions.
8 . The semiconductor device of claim 1 , further comprising: first contacts on the plurality of first doped regions, respectively, and electrically connected to the plurality of first doped regions, respectively; a second contact on the second doped region and electrically connected to the second doped region; and a third contact on the third doped region and electrically connected to the third doped region.
9 . The semiconductor device of claim 8 , further comprising: a second doped pattern penetrating the second doped region and electrically connected to the second contact; and a third doped pattern penetrating the third doped region and electrically connected to the third contact.
10 . The semiconductor device of claim 9 , wherein each of the second doped pattern and the third doped pattern has the second conductivity type, wherein a concentration of dopants having the second conductivity type in the second doped pattern is equal to or greater than a concentration of dopants having the second conductivity type in the second doped region, and wherein a concentration of dopants having the second conductivity type in the third doped pattern is equal to or greater than a concentration of dopants having the second conductivity type in the third doped region.
11 . The semiconductor device of claim 1 , wherein the first well region comprises: a first portion having a first width in the first direction; and a second portion having a second width in the first direction, wherein the first width and the second width are different from each other, wherein some of the plurality of first doped regions are in the first portion of the first well region, and wherein others of the plurality of first doped regions are in the second portion of the first well region.
12 . A semiconductor device comprising: a semiconductor body having a first surface and a second surface, which are opposite to each other, wherein the semiconductor body comprises: a first well region having a first conductivity type; a second well region and a third well region, which are spaced apart from each other in a first direction with the first well region interposed therebetween and have a second conductivity type different from the first conductivity type; a plurality of first doped regions spaced apart from each other in a second direction intersecting the first direction in the first well region, the plurality of first doped regions having the first conductivity type; first contacts on the plurality of first doped regions, respectively; a second doped region, which is adjacent to the second well region and has the second conductivity type; and a third doped region, which is adjacent to the third well region and has the second conductivity type, wherein the second well region is between the first well region and the second doped region, and the third well region is between the first well region and the third doped region, wherein the first surface of the semiconductor body comprises top surfaces of the first to third well regions, the plurality of first doped regions, the second doped region and the third doped region, and wherein the second surface of the semiconductor body comprises bottom surfaces of the first to third well regions, the plurality of first doped regions, the second doped region and the third doped region.
13 . The semiconductor device of claim 12 , wherein a concentration of dopants having the first conductivity type in each of the plurality of first doped regions is greater than a concentration of dopants having the first conductivity type in the first well region, wherein a concentration of dopants having the second conductivity type in the second doped region is greater than a concentration of dopants having the second conductivity type in the second well region, and wherein a concentration of dopants having the second conductivity type in the third doped region is greater than a concentration of dopants having the second conductivity type in the third well region.
14 . The semiconductor device of claim 13 , further comprising: a plurality of first doped patterns penetrating the plurality of first doped regions, respectively, and spaced apart from each other in the second direction, wherein the plurality of first doped patterns are connected to the first contacts, respectively, wherein the plurality of first doped patterns have the first conductivity type, and wherein a concentration of dopants having the first conductivity type in each of the plurality of first doped patterns is equal to or greater than the concentration of the dopants having the first conductivity type in each of the plurality of first doped regions.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0043345, filed on Apr. 7, 2022, and Korean Patent Application No. 10-2022-0131369, filed on Oct. 13, 2022, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. BACKGROUND OF THE INVENTION The present disclosure relates to a semiconductor device including a bipolar junction transistor. A semiconductor device may include an integrated circuit including metal-oxide-semiconductor (MOS) field effect transistors (MOSFETs) and upper interconnection lines connected to the MOS field effect transistors. The MOS field effect transistors and the upper interconnection lines may be disposed on a top surface of a semiconductor substrate. As a size and a design rule of semiconductor devices have been reduced, the MOS field effect transistors and the upper interconnection lines have been scaled down. Operating characteristics of semiconductor devices may be diminished by the scale-down of the MOS field effect transistors and the upper interconnection lines. Thus, various methods for forming a semiconductor device, which has desirable performance characteristics while overcoming limitations caused by high integration have been studied. For example, a semiconductor device may further include lower interconnection lines disposed on a bottom surface of the semiconductor substrate, and a through-electrode penetrating the semiconductor substrate and connecting the lower interconnection lines to the MOS field effect transistors and the upper interconnection lines. A reduction in thickness of the semiconductor substrate may be required to form the through-electrode, and in this case, an operable bipolar junction transistor structure compatible with the through-electrode may be desired. SUMMARY Embodiments of the inventive concepts may provide a semiconductor device including a bipolar junction transistor capable of being realized in a relatively thin semiconductor body. Embodiments of the inventive concepts may also provide a semiconductor device including a bipolar junction transistor capable of relatively easy control of operating characteristics. In an aspect, a semiconductor device may include a semiconductor body having a first surface and a second surface which are opposite to each other. The semiconductor body may include a first well region having a first conductivity type: a second well region and a third well region, which are spaced apart from each other in a first direction with the first well region interposed therebetween and have a second conductivity type different from the first conductivity type; a plurality of first doped regions spaced apart from each other in a second direction intersecting the first direction in the first well region, the plurality of first doped regions having the first conductivity type, wherein a concentration of dopants having the first conductivity type in each of the plurality of first doped regions is greater than a concentration of dopants having the first conductivity type in the first well region; a second doped region, which is adjacent to the second well region and has the second conductivity type; and a third doped region, which is adjacent to the third well region and has the second conductivity type. The second well region may be disposed between the first well region and the second doped region, and the third well region may be disposed between the first well region and the third doped region. The second surface of the semiconductor body may include bottom surfaces of the first to third well regions, the plurality of first doped regions, the second doped region, and the third doped region. In an aspect, a semiconductor device may include a semiconductor body having a first surface and a second surface, which are opposite to each other. The semiconductor body may include a first well region having a first conductivity type: a second well region and a third well region, which are spaced apart from each other in a first direction with the first well region interposed therebetween and have a second conductivity type different from the first conductivity type; a plurality of first doped regions spaced apart from each other in a second direction intersecting the first direction in the first well region, the plurality of first doped regions having the first conductivity type; first contacts on the plurality of first doped regions, respectively; a second doped region, which is adjacent to the second well region and has the second conductivity type; and a third doped region, which is adjacent to the third well region and has the second conductivity type. The second well region may be between the first well region and the second doped region, and the third well region may be between the first well region and the third doped region. The first surface of the semiconductor