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US-12622007-B1 - Type I-II transistor with a manufacturable ledge

US12622007B1US 12622007 B1US12622007 B1US 12622007B1US-12622007-B1

Abstract

A transistor comprising a plurality of semiconductor layers arranged to form a base, an emitter and a collector wherein the emitter is of a first semiconductor material and comprises an emitter ledge being made from a material which is selectively etchable relative to the emitter or base material to produce the emitter ledge that is lattice matched.

Inventors

  • Lawrence E. TAROF
  • Barry Wu
  • Dhiraj Kumar
  • Milton Feng

Assignees

  • ELECTROPHOTONIC-IC INC.

Dates

Publication Date
20260505
Application Date
20250721

Claims (20)

  1. 1 . A heterojunction bipolar transistor comprising a plurality of semiconductor layers, selected from an InP-based materials system, arranged to form a base, an emitter and a collector wherein the emitter has a graded emitter structure comprising an emitter ledge, the emitter ledge comprising a layer of an etch selective material which is selectively etchable relative to at least one of the materials of the emitter and the base: wherein the collector and the emitter comprise InP, the base comprises GaAsSb, the emitter ledge comprises InAIP, and wherein the etch selective material is of the emitter ledge and is selected from a set of Al containing quaternary semiconductor materials (Al-Q) of said InP-based materials system, having a conduction band-similar to a point in the emitter layer at a ledge etch point for a specific composition of InAlP.
  2. 2 . The transistor of claim 1 , wherein materials of the emitter ledge and the emitter are substantially lattice matched.
  3. 3 . The transistor of claim 1 , wherein a position of the etch selective material within the emitter material is where a conduction band of the emitter is matched with a conduction band of the Al-Q material.
  4. 4 . The transistor of claim 1 , wherein the emitter ledge comprises a bulk material or a superlattice material.
  5. 5 . The transistor of claim 4 , wherein the superlattice material comprises a chirped superlattice.
  6. 6 . The transistor of claim 1 , wherein the etch selective material is located intermediate the graded emitter structure to form the emitter ledge.
  7. 7 . The transistor of claim 1 , wherein the emitter ledge has a predetermined bandgap energy profile including one or more of: at least two sloped regions separated by an intermediate region (“notch”) of the emitter ledge.
  8. 8 . The transistor of claim 1 , wherein the emitter ledge comprises a graded emitter comprising a lightly doped AlInP layer and the etch selective material extends through the lightly doped AlInP layer.
  9. 9 . The transistor of claim 1 , wherein the base material comprises GaAs(x)Sb(1-x).
  10. 10 . The transistor of claim 1 , wherein the graded emitter comprises In(1-x)Al(x)P, the etch selective material is InGaAlAs and the etch selective material is sandwiched between the In(1-x)Al(x)P.
  11. 11 . The transistor of claim 1 , wherein the layers on at least one side of the emitter ledge comprise GaAs(x)Sb(1-x) or other arsenide-based material.
  12. 12 . The transistor of claim 11 , wherein the layers of arsenide-based material are on either side of the emitter ledge.
  13. 13 . The transistor of claim 1 , wherein the transistor is a transistor of one of a Transimpedance Amplifier (TIA) in an optical receiver and an Electro-Absorption Modulator (EAM) driver in an optical transmitter.
  14. 14 . An electro-photonic device comprising one of a monolithically integrated photodiode (PD); a monolithically integrated Electro-Absorption Modulator (EAM) or a monolithically integrated Mach-Zehnder modulator (MZM) and electronics comprising a transistor according to claim 1 .
  15. 15 . The electro-photonic device of claim 14 , wherein the device is a receiver and wherein the transistor comprises a Transimpedance Amplifier (TIA).
  16. 16 . The electro-photonic device of claim 15 , wherein an epitaxial layer stack is formed on a semi-insulating (SI) InP substrate; the TIA comprises heterojunction bipolar transistors (HBT) formed by a first plurality of semiconductor layers of the epitaxial layer stack formed on the SI substrate; the PD comprises a p-i-n diode (PIN) formed by a second plurality of semiconductor layers of the epitaxial layer stack overlying the first plurality of semiconductor layers, the second plurality of semiconductor layers comprising an n-layer, an i-layer and a p-layer; and a p-contact of the PIN diode is directly interconnected by a conductive trace to an input of the TIA.
  17. 17 . The electro-photonic device of claim 16 further comprising a spacer comprising one or more intermediate layers comprising a semi-insulating layer between the first plurality of semiconductor layers and the second plurality of semiconductor layers.
  18. 18 . The electro-photonic device of claim 17 , wherein the TIA is formed on a first area of the substrate, and the PIN is provided on an adjacent area and comprising an isolation region electrically isolating the first plurality of semiconductor layers of the first area from the first plurality of semiconductor layers of the adjacent area.
  19. 19 . The electro-photonic device of claim 14 , wherein the device is a transmitter and wherein the transistor comprises a transistor of an Electro-Absorption Modulator (EAM) driver.
  20. 20 . The electro-photonic device of claim 19 , further comprising a plurality of semiconductor layers formed on a semi-insulating (SI) substrate, the plurality of semiconductor layers comprising a first plurality of semiconductor layers defining an optical waveguide forming at least part of the EAM; and a second plurality of semiconductor layers comprising EAM driver layers.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims the benefit of U.S. provisional patent application No. 63/822,383 entitled “A TYPE I-II TRANSISTOR WITH A MANUFACTURABLE LEDGE” filed on Jun. 12, 2025 and is related to U.S. provisional patent application No. 63/822,340 entitled “A TYPE I-II TRANSISTOR FOR HIGH-SPEED APPLICATIONS” filed on Jun. 12, 2025. FIELD OF THE INVENTION The present invention relates generally to a type I-II transistor with a manufacturable ledge, particularly but not exclusively to a Double Heterojunction Bipolar Transistor (DHBT). BACKGROUND A DHBT is a type of bipolar junction transistor (BJT) that uses different semiconductor materials for the emitter and base regions, creating a heterojunction. DHBTs can be made of different types of semiconductor materials. This is particularly the case as data communication technology advances, and speed of operation continues to be pushed beyond the current norms, e.g. next generation high-speed modulation schemes 112 GB, 224 Gb/s PAM4 modulation, 224 GB, 448 Gb/s PAM4 modulation applications, any high-speed data interconnects within data centers and between data centers, passive optical networks (PON), 5G network communications (i.e. optical core network connected to 5G wireless access) and the like. Many different type of transistors have been suggested in the art, and many suffer from inherent problems. Seeking a high-speed transistor has led to various proposals. Si-based HBT (SiGe) and III-V based HBT suffer from gain (β) problems which has mean that they are not suitable for high-speed applications. In III-V compound semiconductors there is a differentiation between Type-I and Type-II transistors, based on the difference of conduction band energy Ec between the emitter and the base layers which also affects performance at high-speeds. A semiconductor heterojunctions behaves based on the alignment of the energy bands at an interface between materials and thus on energy band offsets. The interfaces of such heterojunctions can be categorized in three types: straddling gap (referred to as type I), staggered gap (type II), and broken gap (type III). In some cases, use of Type-I and Type-II transistors have been used but problems have been encountered. Pure Type II transistors have a drawback of electron blocking from the emitter to the base. M.Feng, B. Wu et al. proposed a Type I-II transistor to alleviate this drawback relying on a graded composition Indium Aluminum Phosphide InAIP emitter-base connection. This suffers from further problems including but not limited to fabrication problems, maintaining an acceptable conduction band alignment and ensuring gain is at a level which works in high-speed applications. There is also a suggestion of etching a ledge into the emitter layer for passivation of the extrinsic base surface between the emitter mesa and the base contact metal. The consistent manufacture of such a ledge has proved to be difficult to manufacture and reproduce consistently. Another important factor in transistors for high-speed applications is in ensuring there is an optimal relationship between current gain cutoff frequency (fT) and breakdown voltage (BV). The curve (often referred to as the “Johnson Curve”) of BV against fT needs to reach a higher contour than is possible with CMOS- and Si-technology-based materials. Accordingly, it is interesting for high-speed applications to use Type-I and/or Type-II transistors. A still further factor is the use of different materials in an integrated monolithic device, for example, as used in integrated photonics and electronics devices. These can be made of different materials including but not limited to InP based materials. InP based devices tend to outperform SiGe based devices in many situations, and it is known there are difficulties in making devices combining InP and SiGe based materials. As a result, a monolithic device including photonics and electronics in InP is a sought combination. There are continued problems in overcoming the requirements needed for optimal operation of Type-I and Type-II DHBTs using appropriate materials in high-speed applications. For the avoidance of doubt the nature of high-speed applications includes, but are not limited to high-speed modulation schemes such as 112 GB, 224 Gb/s PAM4 modulation, 224 GB, 448 Gb/s PAM4 modulation applications, any high-speed data interconnects within data centers and between data centers, passive optical networks (PON), 5G network communications (i.e. an optical core network connected to 5G wireless access) and the like. BRIEF SUMMARY The present invention addresses an improved DHBT which overcomes or mitigates at least some of the problems with known approaches and which is suitable next generation high-speed modulation schemes 112 Gb/s, 224 Gb/s PAM4 modulation, 224 Gb/s, 448 Gb/s PAM4 modulation applications, any high-speed data interconnects within data centers and between data centers, passive optica