US-12622008-B2 - III-Nitride/gallium oxide based high electron mobility transistors

Abstract

High electron mobility transistors are provided which comprise a III-Nitride semiconductor layer comprising a III-Nitride semiconductor, in contact with a gallium oxide semiconductor layer comprising gallium oxide, forming an interface therebetween.

Inventors

• Manijeh Razeghi

Assignees

• NORTHWESTERN UNIVERSITY

Dates

Publication Date

20260505

Application Date

20220907

Claims (18)

1. 1 . A high electron mobility transistor comprising a III-Nitride semiconductor layer comprising a III-Nitride semiconductor, in contact with a gallium oxide semiconductor layer comprising gallium oxide, forming an interface therebetween, wherein the high electron mobility transistor further comprises an electrode operably connected to the interface and the high electron mobility transistor is configured to induce formation of a two-dimensional electron gas (2DEG) at the interface between the III-Nitride semiconductor layer and the gallium oxide semiconductor layer upon application of a voltage to the electrode, wherein the III-Nitride semiconductor layer comprises a first sublayer comprising AlN and a second sublayer comprising AlGaN.
2. 2 . The high electron mobility transistor of claim 1 , wherein the III-Nitride semiconductor layer comprises AlGaN, AlN, or both.
3. 3 . The high electron mobility transistor of claim 1 , wherein the III-Nitride semiconductor layer consists of the first and second sublayers.
4. 4 . The high electron mobility transistor of claim 1 , further comprising a substrate, wherein the gallium oxide semiconductor layer is between the III-Nitride semiconductor layer and the substrate.
5. 5 . The high electron mobility transistor of claim 1 , wherein the transistor is free of any other semiconductor other than one or more types of the III-Nitride semiconductor and the gallium oxide.
6. 6 . A method of forming the high electron mobility transistor of claim 1 , the method comprising exposing a substrate positioned in a metalorganic chemical vapor deposition reactor to a III precursor and a nitrogen precursor under conditions to grow the III-Nitride semiconductor of the III-Nitride semiconductor layer; and exposing the substrate to a Ga precursor, an oxygen precursor, and a IV precursor under conditions to grow the gallium oxide of the gallium oxide semiconductor layer.
7. 7 . A method of using the high electron mobility transistor of claim 1 , the method comprising applying the voltage to the electrode.
8. 8 . A high electron mobility transistor comprising a III-Nitride semiconductor layer comprising a III-Nitride semiconductor, in contact with a gallium oxide semiconductor layer comprising gallium oxide, forming an interface therebetween, wherein the high electron mobility transistor further comprises an electrode operably connected to the interface and the high electron mobility transistor is configured to induce formation of a two-dimensional electron gas (2DEG) at the interface between the III-Nitride semiconductor layer and the gallium oxide semiconductor layer upon application of a voltage to the electrode, wherein the gallium oxide is κ-Ga 2 O 3 .
9. 9 . A high electron mobility transistor comprising a III-Nitride semiconductor layer comprising a III-Nitride semiconductor, in contact with a gallium oxide semiconductor layer comprising gallium oxide, forming an interface therebetween, wherein the high electron mobility transistor further comprises an electrode operably connected to the interface and the high electron mobility transistor is configured to induce formation of a two-dimensional electron gas (2DEG) at the interface between the III-Nitride semiconductor layer and the gallium oxide semiconductor layer upon application of a voltage to the electrode, wherein the gallium oxide semiconductor layer is doped with a group IV element.
10. 10 . The high electron mobility transistor of claim 9 , wherein the group IV element is Si.
11. 11 . A high electron mobility transistor comprising a III-Nitride semiconductor layer comprising a III-Nitride semiconductor, in contact with a gallium oxide semiconductor layer comprising gallium oxide, forming an interface therebetween, wherein the high electron mobility transistor further comprises an electrode operably connected to the interface and the high electron mobility transistor is configured to induce formation of a two-dimensional electron gas (2DEG) at the interface between the III-Nitride semiconductor layer and the gallium oxide semiconductor layer upon application of a voltage to the electrode, wherein the gallium oxide semiconductor layer consists of Si-doped Ga 2 O 3 .
12. 12 . A high electron mobility transistor comprising a III-Nitride semiconductor layer comprising a III-Nitride semiconductor, in contact with a gallium oxide semiconductor layer comprising gallium oxide, forming an interface therebetween, wherein the high electron mobility transistor further comprises an electrode operably connected to the interface and the high electron mobility transistor is configured to induce formation of a two-dimensional electron gas (2DEG) at the interface between the III-Nitride semiconductor layer and the gallium oxide semiconductor layer upon application of a voltage to the electrode, further comprising a substrate, wherein the III-Nitride semiconductor layer is between the gallium oxide semiconductor layer and the substrate.
13. 13 . The high electron mobility transistor of claim 12 , wherein the III-Nitride semiconductor layer comprises a first sublayer of AlN and a second sublayer of AlGaN and the second sublayer of AlGaN forms the interface with the gallium oxide semiconductor layer.
14. 14 . The high electron mobility transistor of claim 13 , wherein the gallium oxide semiconductor layer is doped with Si and the gallium oxide is κ-Ga 2 O 3 .
15. 15 . The high electron mobility transistor of claim 14 , wherein the III-Nitride semiconductor layer consists of the first and second sublayers and the gallium oxide semiconductor layer consists of Si-doped Ga 2 O 3 .
16. 16 . The high electron mobility transistor of claim 15 , wherein the transistor is free of any other semiconductor other than AlN, AlGaN, and Ga 2 O 3 .
17. 17 . The high electron mobility transistor of claim 13 , wherein X-ray diffraction peaks associated with the second sublayer of AlGaN of the III-Nitride semiconductor layer and X-ray diffraction peaks associated with the gallium oxide are each characterized by a full-width at half maximum of no more than 1°.
18. 18 . The high electron mobility transistor of claim 12 , wherein the III-Nitride semiconductor layer has a thickness in a range of from 450 nm to 650 nm.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims priority to U.S. provisional patent application No. 63/243,802 that was filed Sep. 14, 2021 and to U.S. provisional patent application No. 63/290,265 that was filed Dec. 16, 2021, the entire contents of both of which are incorporated herein by reference. REFERENCE TO GOVERNMENT RIGHTS This invention was made with government support under FA9550-19-1-0410 awarded by the Air Force Office of Scientific Research. The government has certain rights in the invention. BACKGROUND Growing attention has been given to materials to be utilized for future power devices such as high-power solid-state sources, radio frequency (RF) power transistors, high-power per element phased arrays, and power amplifiers. III-Nitride materials are generally utilized for the aforementioned power devices and III-Nitride based high electron mobility transistors (HEMTs) have demonstrated excellent power performance and high-frequency characteristics. SUMMARY Provided are high electron mobility transistors (HEMTs) comprising a III-Nitride semiconductor (e.g., AlGaN) that forms an interface with a gallium oxide (e.g., κ-Ga2O3) semiconductor. Compared with the theoretically calculated breakdown electric field of 3.14 MV/cm for gallium nitride (GaN), gallium oxide (Ga2O3) has a much higher value of 8 MV/cm. However, RF devices fabricated solely on Ga2O3 face limited performance in view of the low thermal conductivity of the material. Combining Ga2O3 with a III-Nitride semiconductor (e.g., AlN) is intriguing, but presents significant practical challenges that, until the present disclosure, have not been overcome due to the dissimilar nature of the two semiconductor materials. The Example of the present disclosure demonstrates how these challenges have been met to provide HEMTs that exhibit very high electron Hall mobilities, e.g., more than 360 cm2V−1 s−1 (see Table 1). High electron mobility transistors are provided. In embodiments, such a transistor comprises a III-Nitride semiconductor layer comprising a III-Nitride semiconductor, in contact with a gallium oxide semiconductor layer comprising gallium oxide, forming an interface therebetween. Devices comprising the high electron mobility transistors are also provided. Methods of forming and using the high electron mobility transistors are also provided. Other principal features and advantages of the disclosure will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims. BRIEF DESCRIPTION OF DRAWINGS Illustrative embodiments of the disclosure will hereafter be described with reference to the accompanying drawings. FIG. 1A shows an energy band diagram of an AlN/β-Ga2O3 HEMT. FIG. 1B show a plot of carrier density in the two-dimensional electron gas (2DEG) formed at the AlN/β-Ga2O3 interface as a function of barrier thickness and Al/Ga ratio. FIG. 2A shows a cross-sectional view of a III-Nitride/gallium oxide HEMT. FIGS. 2B and 2C show the I-V and transfer characteristics for the HEMT. FIG. 3 shows a schematic of Type 1 and Type 2 HEMT heterostructures that were grown using MOCVD. FIG. 4A shows the XRD spectrum for a Type 1 HEMT heterostructure. FIG. 4B shows the XRD spectrum for a Type 2 HEMT heterostructure prior to annealing (κ-Ga2O3). FIG. 4C shows the XRD spectrum for a Type 2 HEMT heterostructure after annealing (β-Ga2O3). FIG. 5A-5C show the cross-sectional SEM images for the heterostructures of FIGS. 4A-4C, including Type 1 (FIG. 5A), Type 2 prior to annealing (FIG. 5B), and Type 2 after annealing (FIG. 5C). DETAILED DESCRIPTION Provided are high electron mobility transistors (HEMTs). The HEMTs comprise a a III-Nitride semiconductor layer and a gallium oxide semiconductor layer which are in contact with one another, thereby forming an interface between the two layers. The term “III” refers to a group III element such as aluminum (Al), gallium (Ga), and indium (In). In embodiments, the group III element is Al, Ga, or a combination thereof. If a combination of different group III elements is used, e.g., Al and Ga, they may be present in any ratio. For example, in the III-Nitride semiconductor AlGaN (which may also be referred to as AlxGa1-xN), x may range from 0.1 to 0.9, from 0.1 to 0.6, or from 0.2 to 0.5. The III-Nitride semiconductor layer may be in the form of a single layer of a single type of III-Nitride semiconductor, e.g., AlN. However, in embodiments, the III-Nitride semiconductor layer is in the form of multiple (e.g., 2, 3, 4, or more) sublayers of different types of III-Nitride semiconductors, e.g., a AlN sublayer and an AlGaN sublayer. As noted above, the Al and Ga may be present in any ratio in the AlGaN sublayer. The III-Nitride semiconductor layer (and any sublayers) may be undoped. In embodiments, the III-Nitride semiconductor layer consists of one or more types of III-Nitride semiconductors, i.e., no other elements or semicon