US-12622009-B2 - DMOS device having junction field plate and manufacturing method therefor

US12622009B2US 12622009 B2US12622009 B2US 12622009B2US-12622009-B2

Abstract

The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.

Inventors

Feng Lin
Chaoqi XU
Shuxian Chen
Chunxu LI
Li Lu
Siyang Liu
Weifeng Sun

Assignees

CSMC TECHNOLOGIES FAB2 CO., LTD.
SOUTHEAST UNIVERSITY

Dates

Publication Date: 20260505
Application Date: 20221220
Priority Date: 20211231

Claims (20)

1 . A method of manufacturing a DMOS device with a junction field plate, the method comprising: providing a semiconductor substrate, in which a first trench is formed; forming a first doped polycrystalline silicon layer with a first conduction type on the semiconductor substrate, wherein the first doped polycrystalline silicon layer covers a surface of the semiconductor substrate and a surface of the first trench; performing a first doping process and a second doping process on the first doped polycrystalline silicon layer to form a second doped polycrystalline silicon layer on the surface of the semiconductor substrate and a portion of a bottom surface of the first trench, wherein the second doped polycrystalline silicon layer comprises a first doped sublayer with a second conduction type and a second doped sublayer with a first conduction type located on the first doped sublayer; performing a heat treatment process, so that the second doped polycrystalline silicon layer in the first trench extends toward side surfaces of the first trench; removing a portion of the second doped polycrystalline silicon layer to expose a portion of the bottom surface of the first trench; forming a body region at a bottom of the first trench and forming a source region located in the body region; performing a third doping process to form a drain region on the surface of the semiconductor substrate and a third doped sublayer with a second conduction type on a surface of the first doped polycrystalline silicon layer, wherein the second doped polycrystalline silicon layer, the first doped polycrystalline silicon layer, and the third doped sublayer on the side surfaces of the first trench serve as the junction field plate, and the first doped sublayer on the side surfaces of the first trench serves as a gate electrode; and forming a first lead-out structure electrically connected to the source region, a second lead-out structure electrically connected to the drain region and the third doped sublayer, and a third lead-out structure electrically connected to the gate electrode.
2 . The method of manufacturing a DMOS device with a junction field plate according to claim 1 , wherein providing the semiconductor substrate, in which the first trench is formed, comprises: forming a second trench in communication with the first trench in the semiconductor substrate; forming the first doped polycrystalline silicon layer with the first conduction type on the semiconductor substrate, wherein the first doped polycrystalline silicon layer covers the surface of the semiconductor substrate and the surface of the first trench, comprises: the first doped polycrystalline silicon layer covers a surface of the second trench; performing the first doping process and the second doping process on the first doped polycrystalline silicon layer to form the second doped polycrystalline silicon layer on the surface of the semiconductor substrate and the portion of the bottom surface of the first trench, wherein the second doped polycrystalline silicon layer comprises the first doped sublayer with the second conduction type and the second doped sublayer with the first conduction type located on the first doped sublayer, comprises: forming the second doped polycrystalline silicon layer on a portion of a bottom surface of the second trench; performing the heat treatment process, so that the second doped polycrystalline silicon layer in the first trench extends toward the side surfaces of the first trench, comprises: so that the second doped polycrystalline silicon layer in the second trench extends toward side surfaces of the second trench; after forming the body region and the source region located in the body region at the bottom of the first trench, and before performing the third doping process to form the drain region on the surface of the semiconductor substrate and the third doped sublayer with the second conduction type on the surface of the first doped polycrystalline silicon layer, wherein the second doped polycrystalline silicon layer, the first doped polycrystalline silicon layer, and the third doped sublayer on the side surfaces of the first trench serve as the junction field plate, and the first doped sublayer on the side surfaces of the first trench serves as the gate electrode, the method further comprises: removing the first doped polycrystalline silicon layer on the side surfaces of the second trench, wherein the second doped polycrystalline silicon layer in the second trench serves as a gate lead-out layer, and the gate lead-out layer is connected to the gate electrode; and forming the first lead-out structure electrically connected to the source region, the second lead-out structure electrically connected to the drain region and the third doped sublayer, and the third lead-out structure electrically connected to the gate electrode comprises: the third lead-out structure is connected to the gate lead-out layer to achieve electrical connection with the gate electrode.
3 . The method of manufacturing a DMOS device with a junction field plate according to claim 1 , wherein the first conduction type is of a P-type, and the second conduction type is of an N-type; forming the first doped polycrystalline silicon layer with the first conduction type on the semiconductor substrate comprises: forming a polycrystalline silicon layer on the semiconductor substrate; and performing a P-type doping process on the polycrystalline silicon layer to form the first doped polycrystalline silicon layer, wherein a doping concentration for the first doped polycrystalline silicon layer is from 4E14 atom/cm −3 to 1E16 atom/cm −3 , and a thickness of the first doped polycrystalline silicon layer is from 0.15 μm to 0.35 μm.
4 . The method of manufacturing a DMOS device with a junction field plate according to claim 1 , wherein the first conduction type is of a P-type, and the second conduction type is of an N-type; performing the first doping process and the second doping process on the first doped polycrystalline silicon layer comprises: doping phosphonium ions, with a doping concentration from 1E17 atom/cm −3 to 1E18 atom/cm −3 , in the first doping process; and doping indium ions, with a doping concentration from 1E20 atom/cm −3 to 1E21 atom/cm −3 , in the second doping process.
5 . The method of manufacturing a DMOS device with a junction field plate according to claim 2 , wherein performing the heat treatment process, so that the second doped polycrystalline silicon layer in the first trench extends toward the side surfaces of the first trench, further comprises: a diffusion speed of doping ions in the first doping process being faster than that in the second doping process, so that an extension length of the first doped sublayer in the first trench toward the side surfaces of the first trench is greater than that of the second doped sublayer in the first trench toward the side surfaces of the first trench, and an extension length of the first doped sublayer in the second trench toward the side surfaces of the second trench is greater than that of the second doped sublayer in the second trench toward the side surfaces of the second trench.
6 . The method of manufacturing a DMOS device with a junction field plate according to claim 2 , wherein performing the heat treatment process, so that the second doped polycrystalline silicon layer in the first trench extends toward the side surfaces of the first trench, further comprises: the second doped polycrystalline silicon layer on the surface of the semiconductor substrate covers a portion of the side surfaces of the first trench and a portion of the side surfaces of the second trench.
7 . The method of manufacturing a DMOS device with a junction field plate according to claim 2 , wherein removing the portion of the second doped polycrystalline silicon layer to expose the portion of the bottom surface of the first trench comprises: forming a first patterned photoresist layer, wherein the first patterned photoresist layer fills the second trench and extends to cover a portion of the second doped polycrystalline silicon layer on the semiconductor substrate, and another portion of the second doped polycrystalline silicon layer in the first trench and on the semiconductor substrate is exposed; and performing an etching process on a portion of the second doped polycrystalline silicon layer in the first trench and the exposed second doped polycrystalline silicon layer on the semiconductor substrate to remove the portion of the second doped polycrystalline silicon layer in the first trench and the exposed second doped polycrystalline silicon layer on the semiconductor substrate.
8 . The method of manufacturing a DMOS device with a junction field plate according to claim 1 , wherein the first conduction type is of a P-type, and the second conduction type is of an N-type; forming the body region and the source region located in the body region at the bottom of the first trench comprises: performing a P-type doping process on the semiconductor substrate at the bottom of the first trench to form the body region in the semiconductor substrate at the bottom of the first trench; and performing an N-type doping process on a portion of the body region to form the source region in the body region.
9 . The method of manufacturing a DMOS device with a junction field plate according to claim 2 , wherein removing the first doped polycrystalline silicon layer on the side surfaces of the second trench, wherein the second doped polycrystalline silicon layer in the second trench serves as the gate lead-out layer, and the gate lead-out layer is connected to the gate electrode, comprises: filling a hard mask layer in the first trench and the second trench, wherein the hard mask layer extends to cover the second doped polycrystalline silicon layer on the surface of the semiconductor substrate; removing a portion of the hard mask layer by using a wet or dry etching process to expose the second doped polycrystalline silicon layer on the surface of the semiconductor substrate; removing the second doped polycrystalline silicon layer on the surface of the semiconductor substrate by using a dry etching process; forming a second patterned photoresist layer, wherein the second patterned photoresist layer covers the hard mask layer in the first trench and the first doped polycrystalline silicon layer; and removing the first doped polycrystalline silicon layer on the side surfaces of the second trench by using a dry etching process.
10 . A DMOS device with a junction field plate, the device comprising: a semiconductor substrate, in which a first trench is formed; a first doped polycrystalline silicon layer and a second doped polycrystalline silicon layer formed on side walls of the first trench, wherein the second doped polycrystalline silicon layer is closer to a bottom of the first trench than the first doped polycrystalline silicon layer, and the second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer located on the first doped sublayer; a third doped sublayer formed on the side walls of the first trench, wherein the third doped sublayer is closer to a top of the first trench than the first doped polycrystalline silicon layer, the first doped sublayer in the first trench serves as a gate electrode, and the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer, and the third doped sublayer in the first trench serve as the junction field plate, wherein the first doped polycrystalline silicon layer is of a first conduction type, the first doped sublayer is of a second conduction type, the second doped sublayer is of the first conduction type, and the third doped sublayer is of the second conduction type; a body region in the semiconductor substrate formed at the bottom of the first trench and a source region located in the body region; a drain region formed on a surface of the semiconductor substrate; and a first lead-out structure electrically connected to the source region, a second lead-out structure electrically connected to the drain region and the third doped sublayer, and a third lead-out structure electrically connected to the gate electrode.
11 . The DMOS device with a junction field plate according to claim 10 , wherein a second trench in communication with the first trench is further formed in the semiconductor substrate, the second doped polycrystalline silicon layer covers a bottom surface of the second trench, the second doped polycrystalline silicon layer in the second trench serves as a gate lead-out layer, the gate lead-out layer is connected to the gate electrode, and the third lead-out structure is connected to the gate lead-out layer to achieve electrical connection with the gate electrode.
12 . The DMOS device with a junction field plate according to claim 10 , wherein, in the first trench, in a direction from the bottom of the first trench to a trench opening of the first trench, the second doped polycrystalline silicon layer, the first doped polycrystalline silicon layer, and the third doped sublayer are sequentially in adjacent contact and cover side surfaces of the first trench.
13 . The DMOS device with a junction field plate according to claim 10 , wherein the second doped sublayer is located in the first doped sublayer, and in the first trench, a bottom surface of the first doped polycrystalline silicon layer is connected to the first doped sublayer and the second doped sublayer.
14 . The DMOS device with a junction field plate according to claim 11 , wherein, in a first direction, the second trench is in communication with the first trench; in a second direction, the second trench is separated from the first trench, wherein the first direction is perpendicular to the second direction.
15 . The DMOS device with a junction field plate according to claim 10 , wherein the body region surrounds the bottom of the first trench.
16 . The DMOS device with a junction field plate according to claim 11 , wherein, in the first trench, in a direction from the bottom of the first trench to a trench opening of the first trench, the second doped polycrystalline silicon layer, the first doped polycrystalline silicon layer, and the third doped sublayer are sequentially in adjacent contact and cover side surfaces of the first trench.
17 . The DMOS device with a junction field plate according to claim 11 , wherein the second doped sublayer is located in the first doped sublayer, and in the first trench, a bottom surface of the first doped polycrystalline silicon layer is connected to the first doped sublayer and the second doped sublayer.
18 . The DMOS device with a junction field plate according to claim 11 , wherein the body region surrounds the bottom of the first trench.
19 . The DMOS device with a junction field plate according to claim 11 , further comprising: a drift region formed in the semiconductor substrate between the first trench and the second trench.
20 . The DMOS device with a junction field plate according to claim 10 , wherein the first doped sublayer is a doped polycrystalline silicon layer, and doping ions are phosphonium ions, with a doping concentration from 1E17 atom/cm −3 to 1E18 atom/cm −3 ; and the second doped sublayer is a doped polycrystalline silicon layer, and doping ions are indium ions, with a doping concentration from 1E20 atom/cm −3 to 1E21 atom/cm −3 .

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a national stage of international PCT Application No. PCT/CN2022/140340 filed on Dec. 20, 2022, which claims priority to Chinese patent application No. 2021116820195 entitled “DMOS device having junction field plate and manufacturing method therefor” and filed with the Chinese Patent Office on Dec. 31, 2021, entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to the field of semiconductor device technologies, and in particular, to a DMOS device with a junction field plate and its manufacturing method. BACKGROUND Double-diffused Metal-Oxide-Semiconductor (DMOS) devices are typical and widely applied high-voltage power semiconductor devices. By adding a lightly doped drift region between source and drain in a DMOS device, the majority of voltage falls in the lightly doped drift region, so that the voltage resistance capability of the device is improved and the device may be used as a power MOS device in an integrated circuit. According to different structures, the DMOS devices may be divided into two types: Lateral (horizontal) DMOS (LDMOS) devices and Vertical (longitudinal) DMOS (VDMOS) devices. The LDMOS devices are Radio Frequency (RF) power devices with great market demand and broad development prospects. In the field of RF wireless communication, silicon-based LDMOS devices are used in almost all base stations and long-range transmitters. In addition, the LDMOS devices are widely applied to RF amplifiers in High Frequency (HF), Very High Frequency (VHF), and Ultra High Frequency (UHF) communication systems, pulse radar, industrial, scientific and medical applications, avionics, and other fields. Since the LDMOS devices have advantages of high gain, high linearity, high voltage resistance, high output power, easy compatibility with a Complementary Metal Oxide Semiconductor (CMOS) technology, etc., the silicon-based LDMOS devices have become a new hotspot in RF semiconductor power devices. The key to an LDMOS device is to achieve high Breakdown Voltage (BV, which is also referred to as voltage resistance) and low Specific on-Resistance (Rdson). In prior art, the high BV may be achieved only by increasing a size of the drift region, which increases chip area and cost of the LDMOS device. More seriously, a relationship between Rdson and BV of the device may be expressed as Rdson∝BV2.5. That is, increasing the size of the drift region will increase Rdson, which leads to a sharp increase in power consumption, followed by a decrease in device switching speed. Therefore, how to alleviate contradiction between voltage resistance and Rdson, effectively improve voltage resistance or decrease Rdson has become a difficult problem for those skilled in the art to solve urgently. SUMMARY A purpose of the present disclosure is to provide a DMOS device with a junction field plate and its manufacturing method, so as to solve the problem that DMOS devices cannot effectively improve voltage resistance or decrease Rdson in prior art. In order to solve the problem, the present disclosure provides a method for manufacturing a DMOS device with a junction field plate. The method for manufacturing the DMOS device with the junction field plate includes: providing a semiconductor substrate, in which a first trench is formed;forming a first doped polycrystalline silicon layer with a first conduction type on the semiconductor substrate, where the first doped polycrystalline silicon layer covers a surface of the semiconductor substrate and a surface of the first trench;performing a first doping process and a second doping process on the first doped polycrystalline silicon layer to form a second doped polycrystalline silicon layer on the surface of the semiconductor substrate and a portion of a bottom surface of the first trench, where the second doped polycrystalline silicon layer includes a first doped sublayer with a second conduction type and a second doped sublayer with a first conduction type located on the first doped sublayer;performing a heat treatment process, so that the second doped polycrystalline silicon layer in the first trench extends toward side surfaces of the first trench;removing a portion of the second doped polycrystalline silicon layer to expose a portion of the bottom surface of the first trench;forming a body region at a bottom of the first trench and forming a source region located in the body region;performing a third doping process to form a drain region on the surface of the semiconductor substrate and a third doped sublayer with a second conduction type on a surface of the first doped polycrystalline silicon layer, where the second doped polycrystalline silicon layer, the first doped polycrystalline silicon layer, and the third doped sublayer on the side surfaces of the first trench serve as the junction field plate, and the first doped sublayer on the side surfaces of the first trench ser