US-12622010-B2 - Semiconductor device and method for manufacturing semiconductor device

US12622010B2US 12622010 B2US12622010 B2US 12622010B2US-12622010-B2

Abstract

A semiconductor device includes: a substrate; an electron traveling layer provided above the substrate; an electron supply layer provided above the electron traveling layer; gate, source and drain electrodes provided above the electron supply layer; first protrusions that extend from a lower end of the source electrode through an inside of the electron supply layer to below an upper surface of the electron traveling layer; and second protrusions that extend from a lower end of the drain electrode through the inside of the electron supply layer to below the upper surface of the electron traveling layer, wherein a first volume ratio of the first protrusions in a first area where the first protrusions is provided is 60% or less, and a second volume ratio of the second protrusions in a second area where the second protrusions is provided is 60% or less.

Inventors

Yusuke Kumazaki
Naoki Hara
Naoya Okamoto
Shirou Ozaki
Toshihiro Ohki

Assignees

1FINITY INC.

Dates

Publication Date: 20260505
Application Date: 20220818
Priority Date: 20211124

Claims (11)

1 . A semiconductor device comprising: a substrate; an electron traveling layer provided above the substrate; an electron supply layer provided above the electron traveling layer; a gate electrode, a source electrode, and a drain electrode provided above the electron supply layer; a plurality of first protrusions that extend from a lower end of the source electrode through an inside of the electron supply layer to below an upper surface of the electron traveling layer, and that are formed of electrode material of the source electrode; and a plurality of second protrusions that extend from a lower end of the drain electrode through the inside of the electron supply layer to below the upper surface of the electron traveling layer, and that are formed of electrode material of the drain electrode, wherein the plurality of first protrusions extend in a first direction from the source electrode to the drain electrode and are arranged at predetermined intervals in a second direction perpendicular to the first direction, the plurality of second protrusions extend in the first direction and are arranged at predetermined intervals in the second direction, and a first volume ratio of the plurality of first protrusions in a first area where the plurality of first protrusions is provided is 60% or less, and a second volume ratio of the plurality of second protrusions in a second area where the plurality of second protrusions is provided is 60% or less.
2 . The semiconductor device according to claim 1 , wherein the plurality of first protrusions is a plurality of thin plate-shaped protrusions that extend along the first direction that connects the source electrode and the drain electrode in plan view and that are arrayed in the second direction which intersects the first direction in plan view, and the plurality of second protrusions is a plurality of thin plate-shaped protrusions that extend along the first direction and that are arrayed in the second direction.
3 . The semiconductor device according to claim 2 , wherein an end portion on a drain electrode side in the first direction, of the plurality of first protrusions, is offset in a direction away from the drain electrode with respect to an end portion on the drain electrode side in the first direction, of the source electrode, and an end portion on a source electrode side in the first direction, of the plurality of second protrusions, is offset in a direction away from the source electrode with respect to an end portion on the source electrode side in the first direction, of the drain electrode.
4 . The semiconductor device according to claim 3 , wherein an offset amount in the first direction of the plurality of first protrusions is 0 μm to 0.25 μm, both inclusive, and an offset amount in the first direction of the plurality of second protrusions is 0 μm to 0.25 μm, both inclusive.
5 . The semiconductor device according to claim 2 , wherein a bottom surface of the plurality of first protrusions is located at a position of 3 nm to 20 nm, both inclusive, in a depth direction from the upper surface of the electron traveling layer, and a bottom surface of the plurality of second protrusions is located at a position of 3 nm to 20 nm, both inclusive, in the depth direction from the upper surface of the electron traveling layer.
6 . The semiconductor device according to claim 2 , wherein density in the second direction of the plurality of first protrusions in the first area and density in the second direction of the plurality of second protrusions in the second area are 0.2 μm −1 to 5.0 μm −1 , both inclusive.
7 . The semiconductor device according to claim 1 , wherein a semiconductor layer inside the first area or the second area of the electron supply layer or the electron traveling layer has a pit in which metal is embedded, and an element which constitutes the semiconductor layer occupies 80% or more in the semiconductor layer.
8 . The semiconductor device according to claim 1 , wherein the first volume ratio and the second volume ratio are different.
9 . The semiconductor device according to claim 8 , wherein the first volume ratio is 50% or less, and the second volume ratio is higher than 50% and 60% or less.
10 . The semiconductor device according to claim 2 , wherein the first volume ratio is 50% or less, and the second volume ratio is higher than 50% and 60% or less, lengths in the first direction of the first protrusion and the second protrusion are equal, and a width in the second direction of the second protrusion is wider than a width in the second direction of the first protrusion.
11 . A method for manufacturing a semiconductor device comprising: a substrate; forming an electron traveling layer above the substrate; forming an electron supply layer above the electron traveling layer; forming, in a first plane area where a source electrode is formed above the electron supply layer, a plurality of first protrusions that extend through an inside of the electron supply layer to below an upper surface of the electron traveling layer with electrode material of the source electrode; forming, in a second plane area where a drain electrode is formed above the electron supply layer, a plurality of second protrusions that extend through the inside of the electron supply layer to below the upper surface of the electron traveling layer with electrode material of the drain electrode; forming the source electrode and the drain electrode respectively connected to the plurality of first protrusions and the plurality of second protrusions above the electron supply layer; and forming a gate electrode above the electron supply layer, wherein the plurality of first protrusions extend in a first direction from the source electrode to the drain electrode and are arranged at predetermined intervals in a second direction perpendicular to the first direction, the plurality of second protrusions extend in the first direction and are arranged at predetermined intervals in the second direction, and a first volume ratio of the plurality of first protrusions in a first area where the plurality of first protrusions is provided is 60% or less, and a second volume ratio of the plurality of second protrusions in a second area where the plurality of second protrusions is provided is 60% or less.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2021-189997, filed on Nov. 24, 2021, the entire contents of which are incorporated herein by reference. FIELD The embodiments discussed herein are related to a semiconductor device and a method for manufacturing a semiconductor device. BACKGROUND Conventionally, there is a nitride semiconductor device including a nitride semiconductor layer and an ohmic electrode in contact with a side surface of the nitride semiconductor layer, the side surface being a non-polar surface. Unevenness is formed in a surface of the nitride semiconductor layer, and the side surface is a side surface of a recess. The recesses are arranged in a checkered pattern or a stripe shape on the surface of the nitride semiconductor layer. Japanese Laid-open Patent Publication No. 2008-227014 is disclosed as related art. SUMMARY According to an aspect of the embodiments, a semiconductor device includes: a substrate; an electron traveling layer provided above the substrate; an electron supply layer provided above the electron traveling layer; a gate electrode, a source electrode, and a drain electrode provided above the electron supply layer; a plurality of first protrusions that extend from a lower end of the source electrode through an inside of the electron supply layer to below an upper surface of the electron traveling layer, and that are formed of electrode material of the source electrode; and a plurality of second protrusions that extend from a lower end of the drain electrode through the inside of the electron supply layer to below the upper surface of the electron traveling layer, and that are formed of electrode material of the drain electrode, wherein a first volume ratio of the plurality of first protrusions in a first area where the plurality of first protrusions is provided is 60% or less, and a second volume ratio of the plurality of second protrusions in a second area where the plurality of second protrusions is provided is 60% or less. The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. BRIEF DESCRIPTION OF DRAWINGS FIG. 1A is a view illustrating a cross-sectional structure of a semiconductor device 100 of a first embodiment; FIG. 1B is a view illustrating a cross-sectional structure of the semiconductor device 100 of the first embodiment; FIG. 2A is an enlarged perspective view illustrating a part of an inside of the semiconductor device 100; FIG. 2B is a view illustrating a cross-sectional structure of a part of the semiconductor device 100; FIG. 3A is a view illustrating an offset amount X1 of an end portion of a protrusion 160S with respect to a source electrode 150S of the semiconductor device 100; FIG. 3B is a graph illustrating a relationship between the offset amount X1 and a contact resistance Rc; FIG. 4 is a graph illustrating a relationship between a volume ratio of the protrusion 160S in an area 160SA and the contact resistance Rc; FIG. 5A is a view illustrating a position H in a height direction of a bottom surface of the protrusion 160S; FIG. 5B is a graph illustrating a relationship between the position H and the contact resistance Rc; FIG. 6A is a view illustrating a width Wm and an interval Ws of the protrusion 160S; FIG. 6B is a graph illustrating a relationship between density of the protrusion 160S and the contact resistance Rc; FIG. 7A is a view for describing a method for manufacturing the semiconductor device 100; FIG. 7B is a view for describing the method for manufacturing the semiconductor device 100; FIG. 7C is a view for describing the method for manufacturing the semiconductor device 100; FIG. 7D is a view for describing the method for manufacturing the semiconductor device 100; FIG. 7E is a view for describing the method for manufacturing the semiconductor device 100; FIG. 7F is a view for describing the method for manufacturing the semiconductor device 100; FIG. 7G is a view for describing the method for manufacturing the semiconductor device 100; FIG. 7H is a view for describing the method for manufacturing the semiconductor device 100; FIG. 7I is a view for describing the method for manufacturing the semiconductor device 100; FIG. 8A is a view illustrating a cross-sectional structure of a semiconductor device 100A of a second embodiment; FIG. 8B is a view illustrating a cross-sectional structure of the semiconductor device 100A of the second embodiment; FIG. 8C is a view illustrating a cross-sectional structure of a part of the semiconductor device 100A; FIG. 8D is a view for describing a method for manufacturing the semiconductor device 100A of the second embodiment;