US-12622011-B2 - Semiconductor device with diffusion barrier layer and method of fabrication therefor

US12622011B2US 12622011 B2US12622011 B2US 12622011B2US-12622011-B2

Abstract

A semiconductor device includes a semiconductor substrate with an upper surface and a channel, a dielectric layer disposed over the upper surface, and a diffusion barrier layer disposed over the dielectric layer. The diffusion barrier layer is patterned to include multiple segments. A gate electrode is formed over the semiconductor substrate and is electrically coupled to the channel. A drain opening is spatially separated from a first side of the gate electrode. A drain electrode, which also is electrically coupled to the channel, includes a first portion formed within the drain opening, and a second portion that overlies a segment of the diffusion barrier layer. A conductive field plate between the gate electrode and the drain electrode includes a field plate layer and another segment of the diffusion barrier layer. The drain electrode and the field plate layer may be formed from portions of a same conductive layer.

Inventors

Jie Hu

Assignees

NXP USA, INC.

Dates

Publication Date: 20260505
Application Date: 20230411

Claims (20)

1 . A semiconductor device comprising: a semiconductor substrate comprising an upper surface and a channel; a first dielectric layer disposed over the upper surface of the semiconductor substrate; a diffusion barrier layer disposed on and above an upper surface of the first dielectric layer, wherein the diffusion barrier layer is patterned to include multiple segments, including at least a first segment and a second segment; a gate electrode formed over the semiconductor substrate, wherein the gate electrode extends through the first dielectric layer and is electrically coupled to the channel; a drain opening that extends through the first dielectric layer, wherein the drain opening is spatially separated from a first side of the gate electrode; a drain electrode electrically coupled to the channel, wherein the drain electrode includes a first portion formed within the drain opening, and a second portion that overlies the second segment of the multiple segments of the diffusion barrier layer; and a conductive field plate between the gate electrode and the drain electrode, wherein the conductive field plate includes the first segment of the multiple segments of the diffusion barrier layer.
2 . The semiconductor device of claim 1 , wherein: the conductive field plate includes the first segment of the diffusion barrier layer, and a field plate layer on the first segment; and the drain electrode and the field plate layer are formed from portions of a first conductive layer.
3 . The semiconductor device of claim 1 , wherein: sidewalls of the field plate layer are coplanar with sidewalls of the first segment of the multiple segments of the diffusion barrier layer.
4 . The semiconductor device of claim 1 , wherein: a sidewall of the second portion of the drain electrode is coplanar with a sidewall of the second segment of the multiple segments of the diffusion barrier layer.
5 . The semiconductor device of claim 1 , further comprising: a source opening that extends through the first dielectric layer, wherein the source opening is spatially separated from a second side of the gate electrode; and a source electrode electrically coupled to the channel, wherein the source electrode includes a first portion formed within the source opening.
6 . The semiconductor device of claim 5 , wherein: the source electrode further includes a second portion that overlies a third segment of the multiple segments of the diffusion barrier layer.
7 . The semiconductor device of claim 6 , wherein: a sidewall of the second portion of the source electrode is coplanar with a sidewall of the third segment of the multiple segments of the diffusion barrier layer.
8 . The semiconductor device of claim 5 , further comprising: a second dielectric layer disposed over the first dielectric layer; and a connection that extends over a portion of the second dielectric layer and over the gate electrode to electrically connect the field plate to the source electrode.
9 . The semiconductor device of claim 5 , wherein: the conductive field plate includes the first segment of the diffusion barrier layer, and a field plate layer on the first segment; and the drain electrode, the source electrode, and the field plate layer are formed from portions of a first conductive layer.
10 . The semiconductor device of claim 5 , wherein: the gate electrode includes a vertical stem within a gate opening through the first dielectric layer, and first and second protruding regions, which are coupled to the vertical stem and extend over portions of the first dielectric layer toward the source and drain electrodes.
11 . The semiconductor device of claim 1 , wherein: the first dielectric layer is on the upper surface of the semiconductor substrate; the diffusion barrier layer is on the first dielectric layer; and the conductive field plate includes a field plate layer on the first segment.
12 . The semiconductor device of claim 1 , wherein: the diffusion barrier layer is formed from one or more refractory metals, including one or more materials selected from tungsten (W), molybdenum (Mo), and titanium nitride (TiN).
13 . The semiconductor device of claim 1 , wherein: the first dielectric layer is formed from one or more dielectric materials, including one or more materials selected from silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), and hafnium oxide (HfO 2 ).
14 . A gallium nitride field effect transistor device comprising: a semiconductor substrate, comprising gallium nitride and further comprising an upper surface and a channel; a first dielectric layer disposed over the upper surface of the semiconductor substrate; a diffusion barrier layer disposed on and above an upper surface of the first dielectric layer, wherein the diffusion barrier layer is patterned to include first, second, and third segments; a gate electrode formed over the semiconductor substrate, wherein the gate electrode extends through the first dielectric layer and is electrically coupled to the channel; a drain opening that extends through the first dielectric layer, wherein the drain opening is spatially separated from a first side of the gate electrode; a drain electrode electrically coupled to the channel, wherein the drain electrode includes a first portion formed within the drain opening, and a second portion that overlies the second segment of the multiple segments of the diffusion barrier layer; a conductive field plate between the gate electrode and the drain electrode, wherein the conductive field plate includes the first segment of the multiple segments of the diffusion barrier layer; a source opening that extends through the first dielectric layer, wherein the source opening is spatially separated from a second side of the gate electrode; and a source electrode electrically coupled to the channel, wherein the source electrode includes a first portion formed within the source opening, and a second portion that overlies the third segment of the multiple segments of the diffusion barrier layer.
15 . The gallium nitride field effect transistor device of claim 14 , wherein: the conductive field plate includes the first segment of the diffusion barrier layer, and a field plate layer on the first segment; and the drain electrode, the source electrode, and the field plate layer are formed from portions of a first conductive layer.
16 . The gallium nitride field effect transistor device of claim 14 , wherein: a sidewall of the second portion of the drain electrode is coplanar with a sidewall of the second segment of the multiple segments of the diffusion barrier layer; sidewalls of the conductive field plate are coplanar with sidewalls of the first segment of the multiple segments of the diffusion barrier layer; and a sidewall of the second portion of the source electrode is coplanar with a sidewall of the third segment of the multiple segments of the diffusion barrier layer.
17 . A method for forming a semiconductor device, the method comprising: forming a first dielectric layer over an upper surface of a semiconductor substrate that includes a channel; forming a diffusion barrier layer on and above an upper surface of the first dielectric layer; forming a drain opening through the diffusion barrier layer and through the first dielectric layer; depositing a first conductive layer over the diffusion barrier layer and into the drain opening; patterning the first conductive layer and the diffusion barrier layer to form a field plate and a drain electrode that is spatially separated from a first side of the field plate, wherein: the field plate includes a first portion of the first conductive layer and a first segment of the diffusion barrier layer, and the drain electrode includes a second portion of the first conductive layer within the drain opening that is electrically coupled to the channel, and a third portion of the first conductive layer that overlies a second segment of the diffusion barrier layer; and forming a gate electrode over the semiconductor substrate that is spatially separated from a second side of the field plate, wherein the gate electrode extends through the first dielectric layer and is electrically coupled to the channel.
18 . The method of claim 17 , wherein: the diffusion barrier layer is formed from a material selected one or more refractory metals, including one or more materials selected from tungsten (W), molybdenum (Mo), and titanium nitride (TiN).
19 . The method of claim 17 , further comprising: after depositing the first conductive layer and before patterning the first conductive layer and the diffusion barrier layer, performing a high temperature annealing process.
20 . The method of claim 17 , wherein: patterning the first conductive layer and the diffusion barrier layer includes performing an etching process to etch through the first conductive layer; and upon completion of the etching process, sidewalls of the first portion of the first conductive layer are coplanar with sidewalls of the first segment of the diffusion barrier layer, and a sidewall of the third portion of the first conductive layer is coplanar with a sidewall of the second segment of the diffusion barrier layer.

Description

TECHNICAL FIELD Embodiments of the subject matter described herein relate generally to semiconductor devices, and methods for fabricating such devices. BACKGROUND Semiconductor devices find application in a wide variety of electronic components and systems. For example, high power, high frequency transistors find application in radio frequency (RF) systems and power electronics systems. Gallium nitride (GaN) device technology is particularly well suited for these RF power and power electronics applications due to its superior electronic and thermal characteristics. In particular, the high electron velocity and high breakdown field strength of GaN make devices fabricated from this material ideal for RF power amplifiers and high-power switching applications. GaN heterojunction field effect transistors (HFETs) include ohmic source and drain electrodes at opposite ends of a channel, with a gate electrode positioned above the channel between the source and drain electrodes. In addition, some GaN HFETs include a field plate to enhance the performance and reliability of the transistors. High temperature annealing processes performed during fabrication of some GaN HFETs may result in the source and drain electrodes having rough edges (e.g., due to aluminum spiking that may occur during the process). This phenomenon limits the ability to reliably reduce the source-drain pitch for a design, and also may result in mis-alignment of the field plate to the drain electrode. Ultimately, limitations on reducing source-drain pitch and mis-alignment of the field plate and drain electrode may inhibit development of higher-performing GaN HFET designs. Accordingly, there is a need for semiconductor devices and, in particular, GaN devices with higher-quality source and drain electrodes. BRIEF DESCRIPTION OF THE DRAWINGS A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures. FIG. 1 is a cross-sectional, side view of an exemplary transistor, in accordance with an embodiment; FIG. 2 is a process flow diagram for a method for fabricating the transistor of FIG. 1, in accordance with an embodiment; and FIGS. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 are cross-sectional, side views of partially-formed versions of the transistor of FIG. 1 at various stages of fabrication, in accordance with one or more embodiments. DETAILED DESCRIPTION Embodiments of the inventive subject matter described herein include semiconductor devices and methods of their fabrication. More specifically, transistor devices are described herein which include features (e.g., diffusion barrier layer segments) that may enable reduction or elimination of rough edges on source and drain electrodes that may otherwise occur during high temperature annealing processes, if those features are not included. By eliminating such rough edges, the source-drain pitch for a particular transistor design may be reduced. In addition, mis-alignment of a field plate and a drain electrode of a transistor, which may otherwise occur without implementing one or more of the various embodiments disclosed herein, also may be reduced or eliminated. Essentially, transistor embodiments and fabrication methods disclosed herein may enable higher-quality source and drain electrodes, and improved field plate to drain alignment, when compared with many conventional transistors. Although examples of the various embodiments are described below with respect to gallium nitride (GaN) heterojunction field effect transistor (HFET) devices (e.g., device 100, FIG. 1), it should be noted that the various embodiments may be utilized in other types of transistors, transistors that have semiconductor substrates that do not include GaN (i.e., non-GaN-based transistors), and other types of non-transistor semiconductor devices that include features that benefit from high-quality electrodes and accurate alignment of conductive features. Accordingly, the various embodiments described herein are not limited to GaN HFET devices, but instead include transistors other than HFET transistors, non-GaN-based transistors, and semiconductor devices other than transistors. FIG. 1 is a cross-sectional, side view of an exemplary GaN HFET device 100, in accordance with one or more embodiments. GaN HFET device 100 includes a semiconductor substrate 110, one or more isolation regions 120, an active region 125, a first dielectric layer 130, segments of a diffusion barrier layer 138, a source electrode 140 (i.e., “first current-carrying electrode”), a drain electrode 145 (i.e., “second current-carrying electrode”), a gate electrode 150 (i.e., “control electrode”), a field plate 160, and a second dielectric layer 170. Various additional patterned conductive layers and dielectric layers (not shown) may be formed over dielectric layer 170