Search

US-12622012-B2 - Normally-off p-GaN gate double channel HEMT and the manufacturing method thereof

US12622012B2US 12622012 B2US12622012 B2US 12622012B2US-12622012-B2

Abstract

A high electron mobility transistor (HEMT) device including a substrate and a semiconductor stack is provided. The semiconductor stack comprises a lower channel layer, an insertion layer (ISL) positioned above the lower channel layer for confining electrons in the lower channel layer, an upper channel layer, an interface enhancement layer (IEL) positioned above the upper channel layer for confining the electrons in the upper channel layer, and a barrier layer positioned above the IEL. The ISL and the IEL are formed above the lower channel layer and the upper channel layer respectively to create a first and second wide bandgap heterojunction. The ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer. The potential barrier prevents or reduces a flow of hot electrons.

Inventors

  • Jing Chen
  • Hang Liao
  • Zheyang ZHENG
  • Tao Chen

Assignees

  • THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Dates

Publication Date
20260505
Application Date
20230511

Claims (19)

  1. 1 . A high electron mobility transistor (HEMT) device capable of suppressing hot electron induced dynamic on-resistance (RON) degradation, comprising: a substrate; and a semiconductor stack formed on the substrate, comprising: a lower channel layer; an insertion layer (ISL) positioned above the lower channel layer for confining electrons in the lower channel layer; an upper channel layer formed on the ISL and contacting the ISL; an interface enhancement layer (IEL) positioned above the upper channel layer for confining the electrons in the upper channel layer; and a barrier layer positioned above the IEL, wherein: the ISL is formed above the lower channel layer to create a first wide bandgap heterojunction between the lower channel layer and the ISL; the IEL is formed above the upper channel layer to create a second wide bandgap heterojunction between the upper channel layer and the IEL; the ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer; and the potential barrier prevents or reduces a flow of hot electrons moving from the lower channel layer to the barrier layer, wherein the HEMT device further comprises a gate electrode, wherein the semiconductor stack further comprises a p-type cap that is sandwiched between the barrier layer and the gate electrode for realizing a normally-off operation, wherein the p-type cap is provided without a recess-etching into the barrier layer such that the HEMT device has a planar top p-GaN gate and the upper channel layer is a pristine upper channel layer; wherein a thickness of the ISL layer and the IEL layer ranges between 0.5 nm to 2 nm.
  2. 2 . The HEMT device of claim 1 , wherein the lower channel layer is selected from a group consisting GaN, InN, and their alloys; and the ISL is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
  3. 3 . The HEMT device of claim 1 , wherein the upper channel layer is selected from a group consisting GaN, InN, and their alloys; and the IEL is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
  4. 4 . The HEMT device of claim 1 , wherein the barrier layer is a layer of binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
  5. 5 . The HEMT device of claim 1 , wherein the p-type cap is a layer of binary III-N compounds (AlN, GaN, InN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
  6. 6 . The HEMT device of claim 5 , wherein the p-type cap is a p-gallium nitride (p-GaN) cap.
  7. 7 . The HEMT device of claim 5 , further comprising: a plurality of ohmic contacts deposited above the barrier layer to form a source electrode and a drain electrode.
  8. 8 . The HEMT device of claim 7 , wherein a passivation layer is provided above the barrier layer separating the source electrode, the gate electrode, and the drain electrode, wherein the passivation layer is a single layer or a stack of layers selected from AlN/SiN x , AlN/SiO 2 , and SiNx/SiO 2 .
  9. 9 . The HEMT device of claim 7 , wherein the upper channel layer forms a conductive channel for the HEMT device by providing a path for the electrons to flow from the source electrode to the drain electrode with a detour in electron trajectories from the upper channel layer to the lower channel layer, then back to the upper channel layer.
  10. 10 . The HEMT device of claim 1 , wherein the semiconductor stack further comprises a nucleation layer and a buffer layer, wherein the nucleation layer reduces a lattice mismatch between the substrate and the buffer layer; and the buffer layer isolates the nucleation layer from the lower channel layer.
  11. 11 . The HEMT device of claim 10 , wherein the nucleation layer is an III-N nucleation layer selected from a group consisting AlN, GaN, InN, and their alloys.
  12. 12 . The HEMT device of claim 10 , wherein the buffer layer is an III-N semiconductor layer selected from a group consisting AlN, GaN, InN, and their alloys.
  13. 13 . A method for fabricating high electron mobility transistor (HEMT) device capable of suppressing hot electron induced dynamic on-resistance (RON) degradation, the method comprising: preparing a substrate; and forming a semiconductor stack on the substrate, wherein forming the semiconductor stack comprises: forming a lower channel layer; forming an insertion layer (ISL) above the lower channel layer for confining electrons in the lower channel layer, thereby to create a first wide bandgap heterojunction between the lower channel layer and the ISL; forming an upper channel layer on the ISL, wherein the upper channel layer contacts the ISL; forming an interface enhancement layer (IEL) above the upper channel layer for confining the electrons in the upper channel layer, thereby to create a second wide bandgap heterojunction between the upper channel layer and the IEL; and forming a barrier layer above the IEL, wherein: the ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer; and the potential barrier prevents or reduces a flow of hot electrons moving from the lower channel layer to the barrier layer: wherein the method further comprises forming a gate electrode, wherein forming the semiconductor stack further comprises: forming a p-type cap such that the p-type cap is sandwiched between the barrier layer and the gate electrode for realizing a normally-off operation, wherein the p-type cap is provided without a recess-etching into the barrier layer such that the HEMT device has a planar top p-GaN gate and the upper channel layer is a pristine upper channel layer; wherein a thickness of the ISL layer and the IEL layer ranges between 0.5 nm to 2 nm.
  14. 14 . The method of claim 13 , wherein the ISL, the IEL, and the barrier layer are fabricated using material selected from binary III-N compounds (AlN), ternary III-N compounds (AlGaN, InAlN, InGaN), or quaternary III-N compounds (InAlGaN).
  15. 15 . The method of claim 13 , wherein the ISL, the IEL, and the barrier layer are fabricated using AlN, wherein the AlN is formed by MOCVD, MBE, HVPE, plasma-enhanced atomic layer deposition (PEALD) or thermal atomic layer deposition (TALD).
  16. 16 . The method of claim 13 , wherein forming the p-type cap further comprises: forming a p-type layer on the barrier layer by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapour phase epitaxy (HVPE); and removing areas of the p-type layer to obtain the p-type cap by plasma dry etching, digital etching, or a combination thereof, wherein the method further comprises: depositing a passivation layer at the top of the barrier layer and the p-type cap; performing etching from the passivation layer at regions within the p-type cap to create a gate window, and at two opposing sides of the barrier layer to create a source window and a drain window; and depositing a plurality of ohmic contacts at the source window, the drain window, and the gate window to form a source electrode and a drain electrode on the barrier layer, wherein the passivation layer is a single layer or a stack of layers selected from AlN/SiN x , AlN/SiO 2 , and SiNx/SiO 2 .
  17. 17 . The method of claim 16 , wherein the passivation layer is formed by performing plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD).
  18. 18 . The method of claim 13 , wherein the step of forming the semiconductor stack further comprises performing deposition by MOCVD, MBE, or HVPE.
  19. 19 . The method of claim 13 further comprising the step of forming pad metals for establishing connections to the source electrode, the gate electrode, and the drain electrode.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63/352,234 filed on Jun. 15, 2022, the disclosure of which is incorporated by reference herein in its entirety. FIELD OF THE INVENTION The present disclosure generally relates to a semiconductor device. In particular, the present disclosure relates to a normally-off p-gallium nitride (p-GaN) gate double channel high electron mobility transistor (HEMT) and the manufacturing method thereof. BACKGROUND OF THE INVENTION Gallium nitride (GaN) based high-electron-mobility transistors (HEMTs) have gained significant attention in recent years due to their power handling capabilities and superior performance characteristics, such as high switching speed and favorable trade-off between specific on-resistance and breakdown voltage. These properties make GaN HEMTs suitable for a wide range of applications, including switch-mode power converters, LiDARs, and high-frequency power amplifiers. However, the reliability and longevity of these devices are inevitably challenged by hot electrons induced dynamic on-resistance (Ro N) degradation, which results from the simultaneous stress of high electric fields and current densities during operation. Referring to FIG. 1A, a p-GaN single channel HEMT is illustrated. This structure is the main-stream commercialized structure with a Silicon (Si) substrate 10, a GaN buffer layer 20, an aluminum nitride (AlN) barrier 41, an aluminium gallium nitride (AlGaN) barrier layer 40, a dielectric passivation layer 54, a source electrode 51, a gate electrode 52 with a p-GaN layer 55, and a drain electrode 53. With the wide bandgap heterostructure at the GaN buffer layer 20 interfacing with the AlN barrier 41, the device has a two-dimensional electron gas (2 DEG) channel 30 with a high electron mobility. Hot electrons are generated in the 2 DEG channel 30 when the device is hard-switched (VGS>VTH) and features a high drain-source voltage (e.g., 50 V for the device), resulting in elastic scattering of hot electrons. These scattered hot electrons 45 can be redirected toward the critical yet vulnerable interface between the dielectric passivation layer 54 and the AlGaN barrier layer 40 due to high electric fields [1]. Particularly, upon reaching such interface, hot electrons may be captured by pre-existing empty interface traps [2], leading to partial depletion 31 of the 2 DEG channel 30 in the access region and a consequent increase in dynamic RON. The above-described partial depletion 31 is demonstrated in FIG. 1B. Furthermore, the kinetic energy released by hot electrons may result in bombardment of the vulnerable interface region, potentially creating new defects that end up as additional interface traps. These traps are electrically active and can capture electrons but take a long time to release them, leading to further deterioration or degradation of the dynamic RON [3], when the device is subjected to long-term hot electron stress. Conventionally, a surface reinforcement layer (SRL) 46, such as a crystalline (Al)GaON layer, can be deposited over the critical interface between the dielectric passivation layer 54 and the AlGaN barrier layer 40 to prevent damage from the hot electrons [4], as shown in FIG. 2A. The SRL 46 provides an energy barrier to block the hot electrons and physically strengthens the interface to avoid formation of interface traps. This can enhance the reliability of the p-GaN HEMTs under hot electron stress conditions. Alternatively, with reference to FIG. 2B, there are some other approaches to tackle the hot-electron induced dynamic RON degradation issue: 1) by suppressing the generation of hot electrons at the 2 DEG channel 30 or 2) by deterring the generated hot electrons from reaching the critical interface between the dielectric passivation layer 54 and the AlGaN barrier layer 40. The first approach can be realized by employing a field plate, but it requires delicate design to maximize its benefits and to minimize side effects. Accordingly, there is a need in the art for a high-performance GaN HEMT that can effectively suppress hot electron induced dynamic on-resistance degradation. Such a structure would improve the reliability and longevity of the GaN HEMT devices, and enhance their overall performance and market competitiveness. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure. SUMMARY OF THE INVENTION Provided herein is a normally-off p-GaN gate double channel HEMT device and the method for fabricating the same. It is the objective of the present disclosure to provide a HEMT device that can effectively suppress hot electron induced dynamic on-resistance degradation by deterring generated hot electrons from reaching the critical passivation/AlGaN interface. In the