US-12622013-B2 - Folded channel gallium nitride based field-effect transistor and method of manufacturing the same

US12622013B2US 12622013 B2US12622013 B2US 12622013B2US-12622013-B2

Abstract

The folded channel gallium nitride based field-effect transistor includes: a base layer; a multi-heterojunction layer, including a channel layer and a barrier layer alternatingly stacked from bottom to top on a gallium nitride semi-insulating layer; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the channel region; a source electrode and a drain electrode that are respectively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.

Inventors

Sen Huang
Qimeng JIANG
Xinyue DAI
XinHua Wang
Xinyu Liu

Assignees

Institute of Microelectronics, Chinese Academy of Sciences

Dates

Publication Date: 20260505
Application Date: 20230828
Priority Date: 20230421

Claims (8)

1 . A folded channel gallium nitride based field-effect transistor, comprising: a base layer, comprising a nitride buffer layer and a gallium nitride semi-insulating layer formed sequentially on a substrate from bottom to top, wherein a channel region comprising at least one parallel extended groove is formed on an upper surface of the gallium nitride semi-insulating layer; a multi-heterojunction layer, comprising a channel layer and a barrier layer alternatingly stacked from bottom to top on the gallium nitride semi-insulating layer, wherein a heterojunction is formed between the barrier layer and the channel layer that are adjacent; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove, so as to adjust a charge balance within the channel region corresponding to on and off states of the field-effect transistor; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the channel region and separated from the gallium nitride control layer by another part of the groove, wherein the current collapse suppression structure is applicable to provide, when a voltage of a drain electrode is high, a hole injection to the drain electrode, so that a charge balance on the drain electrode is achieved; a source electrode and the drain electrode that are respectively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer, wherein the drain electrode is in contact with a side surface of the current collapse suppression structure and a part of an upper surface of the current collapse suppression structure; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.
2 . The field-effect transistor of claim 1 , wherein, in the multi-heterojunction layer, a thickness of the barrier layer is in a range of 1 nm to 50 nm, and a thickness of the channel layer is in a range of 5 nm to 500 nm; a material of the barrier layer is one of AlN, AlGaN, AlInN, or AlInGaN.
3 . The field-effect transistor of claim 1 , wherein, the gallium nitride control layer comprises a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked from bottom to top, and the current collapse suppression structure comprises a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked from bottom to top; a thickness of the lightly doped P-type gallium nitride layer is in a range of 3 nm to 150 nm, and a thickness of the heavily doped P-type gallium nitride layer is in a range of 5 nm to 30 nm.
4 . The field-effect transistor of claim 1 , wherein, a cross-sectional area of each groove is set as an inverted trapezoid; and an etching angle of a bottom of each groove is set between 90 degrees and 180 degrees; a depth of each groove is in a range of 0.1 μm to 5 μm; and an etching angle of each groove is in a range of 95 degrees to 175 degrees.
5 . The field-effect transistor of claim 1 , wherein, a material of the source electrode is an ohmic contact metal, a material of the drain electrode is an ohmic contact metal, and a material of the gate electrode is a schottky contact metal; the ohmic contact metal comprises at least one of Ti, Al, Ni or Au; the schottky contact metal comprises at least one of Pt, Ti, Al, Ni or TiN.
6 . The field-effect transistor of claim 1 , further comprising: a gate dielectric disposed between the gate electrode and the multi-heterojunction layer, and disposed on the source electrode, the drain electrode, the gallium nitride control layer, the current collapse suppression structure and an exposed multi-heterojunction layer; wherein the gate dielectric comprises one of aluminum oxide, aluminum nitride, silicon oxide or silicon nitride.
7 . The field-effect transistor of claim 1 , further comprising: a passivation dielectric layer formed on the gate dielectric and an exposed multi-heterojunction layer; wherein a material of the passivation dielectric layer is at least one of aluminum oxide, aluminum nitride, silicon oxide or silicon nitride.
8 . The field-effect transistor of claim 1 , wherein an auxiliary groove which matches with a shape of the groove is formed in the multi-heterojunction layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority of Chinese Patent Application No. 202310431333.9 filed on Apr. 21, 2023 in the China National Intellectual Property Administration, the content of which is incorporated herein by reference in entirety. TECHNICAL FIELD At least one embodiment of the present disclosure relates to a field-effect transistor, in particular to a folded channel gallium based field-effect transistor and a method of manufacturing the same. BACKGROUND GaN materials have a large band gap, a high electron saturation rate and a high breakdown electric field, and have a good corrosion resistance, a good radiation resistance and a high thermal conductivity. GaN materials have significant advantages in high-frequency, high-power, radiation, and high-temperature conditions. In addition, an Al (In, Ga)N/GaN heterojunction may spontaneously form two-dimensional electron gas (2DEG) with high concentration and high electron mobility due to strong spontaneous polarization and piezoelectric polarization effects. However, in traditional Al (In, Ga)N/GaN field-effect transistors, it is required to construct a relatively long, low doped N-drift region to ensure that the device has a sufficiently high breakdown voltage. Usually, a size of the low doped N-drift region is higher, a rated value of voltage is higher, but its conduction resistance increases sharply, and a conduction resistance decreases with an increase of voltage, resulting in a decrease in a rated value of current. In addition, in the traditional Al (In, Ga)N/GaN field-effect transistors, an area of the device will be increased with an increase of the size of the low doped N-drift region, thereby increasing a manufacturing cost of the device. SUMMARY In response to the above problems, embodiments of the present disclosure provide a folded channel gallium nitride based field-effect transistor and a method of manufacturing the same, which increase a breakdown voltage of the field-effect transistor and reduces a conduction resistance by increasing a size of a drifting region in a limited field-effect transistor structure. Embodiments of a first aspect of the present disclosure provide a folded channel gallium nitride based field-effect transistor, including: a base layer, including a nitride buffer layer and a gallium nitride semi-insulating layer formed sequentially on a substrate from bottom to top, where a channel region including at least one parallel extended groove is formed on an upper surface of the gallium nitride semi-insulating layer;a multi-heterojunction layer, including a channel layer and a barrier layer alternatingly stacked from bottom to top on the gallium nitride semi-insulating layer, where a heterojunction is formed between the barrier layer and the channel layer that are adjacent;a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove, so as to adjust a charge balance within the channel region corresponding to on and off states of the field-effect transistor;a current collapse suppression structure formed on the multi-heterojunction layer on another side of the channel region and separated from the gallium nitride control layer by another part of the groove; where the current collapse suppression structure is applicable to provide, when a voltage of a drain electrode is high, a hole injection to the drain electrode, so as to effectively release electrons captured near the drain electrode on a surface of the channel, suppress a current collapse effect, and improve dynamic conduction characteristics of the device;a source electrode and the drain electrode that are respectively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer, where the drain electrode is in contact with a side surface of the current collapse suppression structure and a part of an upper surface of the current collapse suppression structure;a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; anda connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer. According to the embodiments of the present disclosure, in the multi-heterojunction layer, a thickness of the barrier layer is in a range of 1 nm to 50 nm, and a thickness of the channel layer is in a range of 5 nm to 500 nm. Preferably, a material of the barrier layer is one of AlN, AlGaN, AlInN, or AlInGaN. According to the embodiments of the present disclosure, the gallium nitride control layer includes a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked from bottom to top, and the current collapse suppression structure includes a lightly doped P-type gallium nitride layer and a heavily doped P-type gallium nitride layer stacked f