US-12622014-B2 - 3D semiconductor device and structure with metal layers and a power delivery path

Abstract

A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, and where the third level is bonded to the second level; a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors; and a plurality of capacitors, where the single crystal first transistors or the second transistors include at least two FinFet transistors, and where two of the at least two FinFet transistors have different threshold voltages (Vt).

Inventors

• Zvi Or-Bach

Assignees

• MONOLITHIC 3D INC.

Dates

Publication Date

20260505

Application Date

20250622

Claims (20)

1. 1 . A 3D semiconductor device, the device comprising: a first level comprising single crystal first transistors, a first metal layer, and a first isolation layer; a second level comprising second transistors and a second isolation layer, wherein said first level is overlaid by said second level; a third level comprising single crystal third transistors, wherein said second level is overlaid by said third level, wherein said third level comprises a third isolation layer, and wherein said third level is bonded to said second level; a power delivery path to said second transistors, wherein at least a portion of said power delivery path is connected to at least one of said first transistors; and a plurality of capacitors, wherein said single crystal first transistors or said second transistors comprise at least two FinFet transistors, and wherein two of said at least two FinFet transistors have different threshold voltages (Vt).
2. 2 . The device according to claim 1 , further comprising: wherein said plurality of capacitors comprises a configuration as a decoupling capacitor to mitigate power supply noise.
3. 3 . The device according to claim 1 , wherein at least one of said second transistors comprises hafnium oxide.
4. 4 . The device according to claim 1 , wherein said second level is bonded to said first level.
5. 5 . The device according to claim 1 , wherein said second level comprises a plurality of DRAM memory cells.
6. 6 . The device according to claim 1 , wherein at least one of said second transistors comprises a two-sided gate.
7. 7 . The device according to claim 1 , wherein said first level comprises at least one digital to analog converter circuit.
8. 8 . A 3D semiconductor device, the device comprising: a first level comprising single crystal first transistors, a first metal layer, and a first isolation layer; a second level comprising second transistors and a second isolation layer, wherein said first level is overlaid by said second level; a third level comprising third transistors; a fourth level comprising a single crystal layer, wherein said second level is overlaid by said third level, wherein said third level is overlaid by said fourth level, wherein said third level comprises a third isolation layer, and wherein said third level is bonded to said second level; and a power delivery path to said second transistors, wherein at least a portion of said power delivery path is connected to at least one of said single crystal first transistors; and wherein said first level comprises power delivery control for at least one of said second transistors.
9. 9 . The device according to claim 8 , further comprising: a plurality of capacitors, wherein said plurality of capacitors comprises a configuration as a decoupling capacitor to mitigate power supply noise.
10. 10 . The device according to claim 8 , further comprising: a thermally conductive path from said second transistors to an external surface of said 3D semiconductor device.
11. 11 . The device according to claim 8 , wherein said second level is bonded to said first level.
12. 12 . The device according to claim 8 , wherein said second level comprises a plurality of DRAM memory cells.
13. 13 . The device according to claim 8 , wherein at least one of said second transistors comprises a two-sided gate.
14. 14 . The device according to claim 8 , wherein said first level comprises at least one digital to analog converter circuit.
15. 15 . A 3D semiconductor device, the device comprising: a first level comprising single crystal first transistors, a first metal layer, and a first isolation layer; a second level comprising second transistors and a second isolation layer, wherein said first level is overlaid by said second level; a third level comprising third transistors; a fourth level comprising a single crystal layer, wherein said second level is overlaid by said third level, wherein said third level is overlaid by said fourth level, wherein said third level comprises a third isolation layer, and wherein said third level is bonded to said second level; and a power delivery path to said second transistors, wherein at least a portion of said power delivery path is connected to at least one of said first transistors, wherein said second level comprises an array of memory cells, wherein each of said memory cells comprise at least one of said second transistors, and wherein said first level comprises control circuits to control data written to said array of memory cells.
16. 16 . The device according to claim 15 , further comprising: a plurality of capacitors, wherein said plurality of capacitors comprises a configuration as a decoupling capacitor to mitigate power supply noise.
17. 17 . The device according to claim 15 , further comprising: a thermally conductive path from said second transistors to an external surface of said 3D semiconductor device.
18. 18 . The device according to claim 15 , wherein said second level is bonded to said first level.
19. 19 . The device according to claim 15 , further comprising: a global power distribution metal layer, wherein said global power distribution metal layer comprises a metal thickness twice as thick as said first metal layer.
20. 20 . The device according to claim 15 , wherein said first level comprises at least one digital to analog converter circuit.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation-in-part of U.S. patent application Ser. No. 18/778,978, filed on Jul. 20, 2024; which is a continuation-in-part of U.S. patent application Ser. No. 18/429,202, filed on Jan. 31, 2024, now U.S. Pat. No. 12,094,965, issued on Sep. 17, 2024; which is a continuation-in-part of U.S. patent application Ser. No. 18/388,852, filed on Nov. 12, 2023, now U.S. Pat. No. 11,935,949, issued on Mar. 19, 2024; which is a continuation-in-part of U.S. patent application Ser. No. 18/227,183, filed on Jul. 27, 2023, now U.S. Pat. No. 11,869,965, issued on Jan. 9, 2024; which is a continuation-in-part of U.S. patent application Ser. No. 18/125,053, filed on Mar. 22, 2023, now U.S. Pat. No. 11,757,030, issued on Sep. 12, 2023; which is a continuation-in-part of U.S. patent application Ser. No. 18/092,727, filed on Jan. 3, 2023, now U.S. Pat. No. 11,677,021, issued on Jun. 13, 2023; which is a continuation-in-part of U.S. patent application Ser. No. 17/961,565, filed on Oct. 7, 2022, now U.S. Pat. No. 11,575,038, issued on Feb. 7, 2023; which is a continuation of U.S. patent application Ser. No. 17/384,992, filed on Jul. 26, 2021, now U.S. Pat. No. 11,515,413, issued on Nov. 29, 2022; which is a continuation of U.S. patent application Ser. No. 17/222,784, filed on Apr. 5, 2021, now U.S. Pat. No. 11,121,246, issued on Sep. 14, 2021; which is a continuation of U.S. patent application Ser. No. 17/176,146, filed on Feb. 15, 2021, now U.S. Pat. No. 11,004,967, issued on May 11, 2021; which is a continuation of U.S. patent application Ser. No. 16/226,628, filed on Dec. 19, 2018, now U.S. Pat. No. 10,964,807, issued on Mar. 30, 2021; which is a continuation of U.S. patent application Ser. No. 15/727,592, filed on Oct. 7, 2017, now U.S. Pat. No. 10,355,121, issued on Jul. 16, 2019; which is a continuation of U.S. patent application Ser. No. 15/351,389, filed on Nov. 14, 2016, now U.S. Pat. No. 9,799,761, issued on Oct. 24, 2017; which is a continuation of U.S. patent application Ser. No. 14/506,160, filed on Oct. 3, 2014, now U.S. Pat. No. 9,496,271, issued on Nov. 15, 2016: which is a continuation of U.S. patent application Ser. No. 13/792,202, which was filed on Mar. 11, 2013, now U.S. Pat. No. 8,902,663, issued on Dec. 2, 2014; the entire contents of all of the foregoing are incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to the field of monolithic 3D integration to semiconductor chips performing logic and/or memory functions. 2. Discussion of Background Art Over the past 40 years, the microelectronic industry has seen a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of “scaling” i.e. component sizes within ICs have been reduced (“scaled”) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With “scaling”, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with “scaling”. The situation today is that wires dominate performance, functionality and power consumption of ICs. 3D stacking of semiconductor chips is one avenue to tackle issues with wires. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990s), one can place transistors in ICs closer to each other. This reduces wire lengths and keeps wiring delay low. However, there are many barriers to practical implementation of 3D stacked chips. These include: Constructing transistors in ICs typically require high temperatures (higher than ˜700° C.) while wiring levels are constructed at low temperatures (lower than ˜400° C.). Copper or Aluminum wiring levels, in fact, can get damaged when exposed to temperatures higher than ˜400° C. If one would like to arrange transistors in 3 dimensions along with wires, it has the challenge described below. For example, let us consider a 2 layer stack of transistors and wires i.e. Bottom Transistor Layer, above it Bottom Wiring Layer, above it Top Transistor Layer and above it Top Wiring Layer. When the Top Transistor Layer is constructed using Temperatures higher than 700° C., it can damage the Bottom Wiring Layer.Due to the above mentioned problem with forming transistor layers above wiring layers at temperatures lower than 400° C., the semiconductor industry has largely explored alternative architectures for 3D stacking. In these alternative architectures, Bottom Transistor Layers, Bottom Wiring Layers and Contacts to the Top Layer are constructed on one silicon wafer. Top Transistor Layers, Top Wiring Layers and Contacts to the Bottom Layer are constructed on another silicon wafer. These two