US-12622015-B2 - Semiconductor devices having variously-shaped source/drain patterns

Abstract

A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

Inventors

• Hyun-Kwan Yu
• Min-Hee Choi

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20240305

Priority Date

20180612

Claims (20)

1. 1 . A method of fabricating a semiconductor device, the method comprising: patterning a substrate to form a first active pattern and a second active pattern, the first active pattern comprising a first sidewall that faces the second active pattern and a second sidewall opposite from the first sidewall; forming a device isolation layer comprising an outer segment and an intermediate segment, the outer segment on the second sidewall, the intermediate segment between the first and second active patterns; forming a sacrificial pattern that crosses the first and second active patterns; forming a mask pattern on the sacrificial pattern; forming a gate spacer on a sidewall of the sacrificial pattern; etching the first and second active patterns, the outer segment, and the intermediate segment using the mask pattern and the gate spacer as an etch mask; and forming a source/drain pattern on the first and second active patterns, wherein an uppermost level of the etched outer segment is lower than a lowermost level of a top surface of the etched intermediate segment.
2. 2 . The method of claim 1 , wherein the etching of the outer segment comprises exposing the second sidewall of the first active pattern.
3. 3 . The method of claim 1 , wherein the source/drain pattern comprises: a first part in contact with the first active pattern; a second part in contact with the second active pattern; and a third part in contact with the first active pattern and the outer segment, wherein the first, second, and third parts of the source/drain pattern are merged with each other, and wherein a lowermost level of the third part of the source/drain pattern is closer to the substrate than the lowermost level of the top surface of the etched intermediate segment.
4. 4 . The method of claim 3 , wherein a void is between the first and second parts of the source/drain pattern.
5. 5 . The method of claim 3 , wherein the first part of the source/drain pattern is in contact with a top surface of the first active pattern, and wherein the third part of the source/drain pattern is in contact with the second sidewall of the first active pattern.
6. 6 . The method of claim 3 , wherein the third part of the source/drain pattern comprises a rounded outer surface.
7. 7 . The method of claim 1 , wherein the first sidewall of the first active pattern is spaced apart from the source/drain pattern.
8. 8 . A method of fabricating a semiconductor device, comprising: patterning a substrate to form a first active pattern and a second active pattern, the first active pattern comprising a first sidewall that faces the second active pattern and a second sidewall opposite from the first sidewall; forming a device isolation layer comprising an outer segment and an intermediate segment, the outer segment covering a lower portion of the second sidewall of the first active pattern and the intermediate segment covering a lower portion of the first sidewall of the first active pattern; forming a sacrificial pattern that crosses the first and second active patterns; forming a mask pattern on the sacrificial pattern; forming a gate spacer on a sidewall of the sacrificial pattern; etching the first and second active patterns, the outer segment, and the intermediate segment using the mask pattern and the gate spacer as an etch mask; and forming a source/drain pattern on the first and second active patterns, wherein a height of a portion of the lower portion of the second sidewall of the first active pattern that is exposed by etching the outer segment is greater than a height of a portion of the lower portion of the first sidewall of the first active pattern that is exposed by etching the intermediate segment, wherein the source/drain pattern comprises: a first part on a top surface of the first active pattern; a second part on a top surface of the second active pattern; and a third part on the portion of the lower portion of the second sidewall of the first active pattern, and wherein a lowermost level of the third part of the source/drain pattern is closer to the substrate than a lowermost level of a top surface of the etched intermediate segment is to the substrate.
9. 9 . The method of claim 8 , wherein the forming of the source/drain pattern comprises performing an epitaxial growth process using the portion of the lower portion of the second sidewall as a seed layer.
10. 10 . The method of claim 8 , wherein the first, second, and third parts of the source/drain pattern are merged with each other, and wherein a top surface of the first part of the source/drain pattern and a top surface of the second part of the source/drain pattern are coplanar.
11. 11 . The method of claim 8 , wherein the lowermost level of the third part of the source/drain pattern is closer to a surface of the substrate than a lowermost level of the portion of the lower portion of the second sidewall of the first active pattern is to the substrate.
12. 12 . The method of claim 8 , wherein a void is between the first and second parts of the source/drain pattern.
13. 13 . The method of claim 8 , wherein the first part of the source/drain pattern is in contact with a top surface of the first active pattern, and wherein the third part of the source/drain pattern is in contact with the second sidewall of the first active pattern.
14. 14 . The method of claim 8 , wherein the third part of the source/drain pattern comprises a rounded outer surface.
15. 15 . The method of claim 8 , wherein the etching of the outer segment comprises exposing the second sidewall of the first active pattern.
16. 16 . The method of claim 8 , wherein the first sidewall of the first active pattern is spaced apart from the source/drain pattern.
17. 17 . A method of fabricating a semiconductor device, comprising: patterning a substrate to form a first active pattern and a second active pattern, the first active pattern comprising a first sidewall that faces the second active pattern and a second sidewall opposite from the first sidewall; forming a device isolation layer comprising an outer segment and an intermediate segment, the outer segment covering a lower portion of the second sidewall of the first active pattern and the intermediate segment covering a lower portion of the first sidewall of the first active pattern; forming a sacrificial pattern that crosses the first and second active patterns; forming a mask pattern on the sacrificial pattern; forming a gate spacer on a sidewall of the sacrificial pattern; etching the first and second active patterns, the outer segment, and the intermediate segment using the mask pattern and the gate spacer as an etch mask; and forming a source/drain pattern on the first and second active patterns, wherein a height of a portion of the lower portion of the second sidewall of the first active pattern that is exposed by etching the outer segment is greater than a height of a portion of the lower portion of the first sidewall of the first active pattern that is exposed by etching the intermediate segment, wherein an uppermost level of the etched outer segment is closer to the substrate than a lowermost level of a top surface of the etched intermediate segment is to the substrate.
18. 18 . The method of claim 17 , wherein the etching of the outer segment comprises exposing the second sidewall of the first active pattern.
19. 19 . The method of claim 17 , wherein the first sidewall of the first active pattern is spaced apart from the source/drain pattern.
20. 20 . The method of claim 17 , wherein the source/drain pattern comprises: a first part in contact with the first active pattern; a second part in contact with the second active pattern; and a third part in contact with the first active pattern and the outer segment, wherein the first, second, and third parts of the source/drain pattern are merged with each other, and wherein a lowermost level of the third part of the source/drain pattern is closer to the substrate than the lowermost level of the top surface of the etched intermediate segment.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 18/196,533, filed on May 12, 2023, which in turn is a continuation of U.S. application Ser. No. 17/131,977, filed on Dec. 23, 2020, which in turn is a continuation of U.S. application Ser. No. 16/252,919, filed on Jan. 21, 2019, which claims the benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2018-0067354, filed on Jun. 12, 2018, in the Korean Intellectual Property Office, and the entire contents of each above-identified application are hereby incorporated by reference. TECHNICAL FIELD The present inventive concepts relate to semiconductor devices, and more particularly, to semiconductor devices having variously shaped source/drain patterns. BACKGROUND Semiconductor devices are beneficial in the electronic industry, and in other industries for many reasons, such as their small size, their multi-functionality, and/or their low fabrication cost. Semiconductor devices may encompass semiconductor memory devices storing logic data, semiconductor logic devices processing operations of logic data, and hybrid semiconductor devices having both memory and logic elements. The advancing development of the electronic industry and other industries has made semiconductor devices with increasing integration increasingly desirable. For example, semiconductor devices having high reliability, high speed, and/or multi-functionality have been increasingly requested. Semiconductor devices are becoming gradually more complicated and more integrated to meet these requested characteristics. SUMMARY The inventive concepts disclosed herein provide semiconductor devices with improved electrical characteristics. According to some example embodiments of the present inventive concepts, a semiconductor device may comprise: a plurality of active patterns on a substrate; a device isolation layer defining the plurality of active patterns; a gate electrode extending across the plurality of active patterns; and a source/drain pattern on the plurality of active patterns. The plurality of active patterns may comprise: a first active pattern; and a second active pattern. The source/drain pattern may comprise: a first part on the first active pattern; a second part on the second active pattern; and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer may comprise a first outer segment on a sidewall of the first active pattern and below the source/drain pattern. A lowermost level of a bottom surface of the third part of the source/drain pattern may be lower than an uppermost level of a top surface of the first outer segment. According to some example embodiments of the present inventive concepts, a semiconductor device may comprise: a plurality of active patterns on a substrate; a device isolation layer defining the plurality of active patterns; a gate electrode extending across the active patterns; and a source/drain pattern on the plurality of active patterns. The plurality of active patterns may comprise first, second, and third active patterns. The second active pattern may be between the first and third active patterns. The source/drain pattern may comprise: a first part on the first active pattern; a second part on the second active pattern; and a third part on the third active pattern. The first, second, and third parts of the source/drain pattern may be merged with each other. A first valley having a first depth may be defined between the first and second parts of the source/drain pattern. A second valley having a second depth may be defined between the second and third parts of the source/drain pattern. The second depth may be less than the first depth. According to some example embodiments of the present inventive concepts, a semiconductor device may comprise: a substrate; first, second, and third active patterns on the substrate; a gate electrode extending across the first, second, and third active patterns; and a source/drain pattern on the first, second, and third active patterns. The source/drain pattern may comprise first, second, and third parts respectively on the first, second, and third active patterns. The first and second parts of the source/drain pattern may be spaced apart from each other. The second and third parts of the source/drain pattern may be merged with each other. A lowermost level of a bottom surface of the second part of the source/drain pattern may be lower than a lowermost level of a bottom surface of the third part of the source/drain pattern. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A, 2A, 3A, and 4A illustrate plan views showing operations in methods of manufacturing semiconductor devices, according to some of the present inventive concepts. FIGS. 1B, 2B, 3B, and 4B illustrate cross-sectional views taken along line A-A′ of FIGS. 1A, 2A, 3A, and 4A, respectively. FIGS. 2C, 3C, and 4C illustrate cross-sectio