US-12622016-B2 - Lateral power semiconductor device

US12622016B2US 12622016 B2US12622016 B2US 12622016B2US-12622016-B2

Abstract

A lateral power semiconductor device is provided and includes a second doping type substrate, a first doping type buried layer, a second doping type epitaxial layer, a first doping type drift area, a second doping type first body area, a first doping type drain area, a first doping type source area, a second doping type second body area, a dielectric layer, a control gate, a body electrode, second doping type polysilicon and first doping type polysilicon. The control gate is led out and connected to different potentials; when the device is in an off state, the control gate is connected to a low potential to assist the drift area in depletion; and when the device is in an on state, the control gate is connected to a high potential, and more carriers are induced on a silicon surface below the control gate.

Inventors

Ming Qiao
Yue Gao
Jiawei WANG
Dingxiang Ma
Bo Zhang

Assignees

UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

Dates

Publication Date: 20260505
Application Date: 20231023
Priority Date: 20230524

Claims (9)

1 . A lateral power semiconductor device, comprising: a second doping type substrate, a first doping type buried layer above the second doping type substrate, a second doping type epitaxial layer above the first doping type buried layer, a first doping type drift area above an interior of the second doping type epitaxial layer, a left-side second doping type first body area and a right-side first doping type drain area inside the first doping type drift area, and a first doping type source area and a second doping type second body area on an inner upper surface of the second doping type first body area, wherein the first doping type source area is adjacent to and short-connected to the second doping type second body area; a dielectric layer is arranged on an upper surface of the first doping type drift area; a source electrode, a main gate, a salicide block (SAB) structure, a control gate and a drain electrode are arranged inside the dielectric layer from left to right; the source electrode is in ohmic contact with the first doping type source area and the second doping type second body area; the main gate is located above the second doping type first body area and the first doping type drift area, and is isolated from a semiconductor silicon through the dielectric layer; the control gate is located above the SAB structure, the SAB structure is located above the first doping type drift area, and the SAB structure is isolated from a surface of the first doping type drift area through the dielectric layer; and the drain electrode is in ohmic contact with the first doping type drain area, wherein a width of the main gate is greater than a length of a channel, wherein an accumulation area is formed on the surface of the first doping type drift area.
2 . The lateral power semiconductor device according to claim 1 , comprising a double gate structure with the control gate and the main gate, wherein a control gate structure is led out and separately connected to a potential; and when the lateral power semiconductor device is in an off state, the main gate is connected to a low potential, the source electrode is connected to the low potential or is grounded, the drain electrode is connected to a high potential, and the control gate provides the low potential.
3 . The lateral power semiconductor device according to claim 1 , wherein when the lateral power semiconductor device is in an on state, the main gate is connected to a high potential, the source electrode is connected to a low potential or is grounded, the drain electrode is connected to the high potential, the control gate is connected to the high potential, and the high potential is in a positive voltage.
4 . The lateral power semiconductor device according to claim 1 , wherein before the main gate is connected to a low potential and the lateral power semiconductor device is switched off, the control gate is connected to the low potential in advance.
5 . The lateral power semiconductor device according to claim 1 , wherein when the lateral power semiconductor device is switched on, the main gate is connected to a high potential, the source electrode is connected to a low potential or is grounded, the drain electrode is connected to the high potential, and an electrode of the control gate is connected to the high potential; before the main gate is connected to the low potential and the lateral power semiconductor device is switched off, the control gate is connected to the low potential in advance; and when the lateral power semiconductor device is switched off, the main gate is connected to the low potential, and the control gate is connected to the low potential.
6 . The lateral power semiconductor device according to claim 1 , wherein a body electrode is arranged on a left side of the source electrode, the source electrode and the body electrode are separate, and the source electrode is connected to different potentials to sample current signals.
7 . The lateral power semiconductor device according to claim 1 , wherein the dielectric layer below the SAB structure and the control gate is in a stepped shape, and the dielectric layer adjacent to a drain terminal is thicker.
8 . The lateral power semiconductor device according to claim 1 , wherein the dielectric layer below the SAB structure and the control gate is in a slope shape, and the dielectric layer is thickened uniformly in a direction from a source terminal to a drain terminal.
9 . The lateral power semiconductor device according to claim 1 , wherein no metal is deposited on the SAB structure, but a second doping type polysilicon and a first doping type polysilicon are deposited on the SAB structure; the second doping type polysilicon and the first doping type polysilicon form the control gate; and in a case that a negative bias voltage is applied to the control gate, a PN junction on the control gate is in a reverse bias state.

Description

CROSS REFERENCE TO THE RELATED APPLICATIONS This application is based upon and claims priority to Chinese Patent Application No. 202310591908.3, filed on May 24, 2023, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present invention belongs to the technical field of power semiconductors, and relates to a lateral power semiconductor device. BACKGROUND In the field of power integrated circuits, power semiconductor devices are widely applied. In particular, in the field of integrated drive circuits, a laterally-diffused metal-oxide semiconductor (LDMOS) plays an indispensable role due to the characteristic of easy integration. A reduce surface field (RESURF) is often used to improve the electrical characteristics of LDMOS. The power LDMOS usually requires low specific on resistance (Ron,sp), large safe operating area (SOA) and high breakdown voltage. The schematic diagram of a traditional LDMOS device is shown in FIG. 1, and a metal field plate is connected to a source electrode. A high-current device usually has large switching loss, which will affect the performance and life of the device. SUMMARY To reduce a switching loss and obtain a high-current low-resistance device, a lateral power semiconductor device with a double gate structure is introduced. As shown in FIG. 2A, the voltage of a control gate when the device is switched off may be separately set, and a negative potential is given to the control gate to make the control gate assist a drift area in depletion, which is conducive to obtaining an expected breakdown voltage at a higher drift area concentration, thereby increasing the on current, reducing Ron,sp, and not reducing the breakdown voltage of the device. However, to avoid hot-carrier effect and advanced breakdown caused by excessively strong electric field modulation effect of the control gate on a silicon surface, the thickness of an insulating dielectric layer under SAB is adjusted to make the dielectric layer close to a drain area thicker, so that the advanced breakdown problem of the device can be effectively relieved, where SAB is salicide block. On the control gate, polysilicon with a PN junction is used, thereby reducing the gate-drain coupling charge number and the equivalent capacitance CGD. Based on the above theoretical analysis, the double gate structure and different dielectric layers introduced by the present invention can adjust the voltage of the control gate to reduce the loss and the specific on resistance of the device, optimize the breakdown voltage of the device and relieve the hot-carrier injection effect. The present invention appears under this background. To achieve the aforementioned objective of the present invention, the technical solution of the present invention is as follows: a lateral power semiconductor device includes: a second doping type substrate 1, a first doping type buried layer 2 above the second doping type substrate 1, a second doping type epitaxial layer 3 above the first doping type buried layer 2, a first doping type drift area 4 above an interior of the second doping type epitaxial layer 3, a left-side second doping type first body area 5 and a right-side first doping type drain area 8 inside the first doping type drift area 4, and a first doping type source area 7 and a second doping type second body area 6 on an inner upper surface of the second doping type first body area 5, where the first doping type source area 7 is adjacent to and short-connected to the second doping type second body area 6; a dielectric layer 13 is arranged on an upper surface of the first doping type drift area 4;a source electrode 9, a main gate 10, a salicide block (SAB) structure 11, a control gate 14 and a drain electrode 12 are arranged inside the dielectric layer 13 from left to right, the source electrode 9 is in ohmic contact with the first doping type source area 7, and the source electrode 9 is in ohmic contact with the second doping type second body area 6; the main gate 10 is located above the second doping type first body area 5 and the first doping type drift area 4, and is isolated from semiconductor silicon through the dielectric layer 13; the control gate 14 is located above the salicide block (SAB) structure 11, the salicide block (SAB) structure 11 is located above the first doping type drift area 4, and the salicide block (SAB) structure 11 is isolated from a surface of the first doping type drift area 4 through the dielectric layer 13; and the drain electrode 12 is in ohmic contact with the first doping type drain area 8. As a preferred manner, the width of the main gate 10 is greater than the length of the channel, so that an accumulation area is formed on the surface of the first doping type drift area 4. The on resistance is reduced, the static characteristic is improved, and the loss of the device is reduced. In a traditional structure, the control gate is deposited on the salicide block (SAB) structure 11 an