US-12622017-B2 - Semiconductor device with multi-layer contact liner structure

Abstract

Provided is a semiconductor device including an active pattern extended in a first direction, a plurality of gate structures including a gate electrode and a gate spacer disposed to be spaced apart from each other in the first direction on the active pattern and extended in a second direction, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a contact liner structure extended along a sidewall of the source/drain contact, being in contact with the sidewall of the source/drain contact. The contact liner structure includes a first contact liner and a second contact liner on the first contact liner. The first contact liner includes a first bottom portion, and a first vertical portion protruded from the first bottom portion and extended in a third direction. A lower surface of the contact liner structure is higher than an upper surface of the source/drain pattern.

Inventors

• Kyu-hee Han
• Bong Kwan Baek
• Jung Hwan CHUN
• Koung Min RYU
• Jong Min Baek
• Jung Hoo Shin
• Jun Hyuk LIM
• SANG SHIN JANG

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20230306

Priority Date

20220607

Claims (20)

1. 1 . A semiconductor device comprising: an active pattern extended in a first direction; a plurality of gate structures comprising a gate electrode and a gate spacer, which are disposed to be spaced apart from each other in the first direction on the active pattern and extended in a second direction; a source/drain pattern on the active pattern; a source/drain contact on the source/drain pattern; and a contact liner structure extended along a sidewall of the source/drain contact, being in contact with the sidewall of the source/drain contact, wherein the contact liner structure comprises a first contact liner and a second contact liner on the first contact liner, wherein the first contact liner comprises a first bottom portion, and a first vertical portion protruded from the first bottom portion and extended in a third direction, wherein a lower surface of the contact liner structure is spaced apart from level of an upper surface of the source/drain pattern, and wherein the sidewall of the source/drain contact extends downwardly beyond the first bottom portion of the first contact liner and a lower end portion of the second contact liner.
2. 2 . The semiconductor device of claim 1 , wherein the second contact liner comprises a material having a dielectric constant smaller than that of the first contact liner.
3. 3 . The semiconductor device of claim 1 , wherein the second contact liner comprises carbon, and wherein a concentration of carbon contained in the second contact liner at a first height in the third direction is higher than a concentration of carbon contained in the second contact liner at a second height lower than the first height.
4. 4 . The semiconductor device of claim 1 , wherein the second contact liner comprises: a second bottom portion on the first bottom portion; and a second vertical portion protruded from the second bottom portion and extended in the third direction.
5. 5 . The semiconductor device of claim 1 , further comprising an etch stop layer extended along a sidewall of the plurality of gate structures and the upper surface of the source/drain pattern, wherein the etch stop layer is in contact with the first vertical portion at a first height in the third direction, and wherein an interlayer insulating layer is disposed between the etch stop layer and the first vertical portion at a second height lower than the first height in the third direction.
6. 6 . The semiconductor device of claim 5 , wherein the plurality of gate structures further include a gate capping layer on the gate electrode and the gate spacer, wherein the etch stop layer is in contact with the gate capping layer at the first height, and wherein the etch stop layer is in contact with the gate spacer at the second height.
7. 7 . The semiconductor device of claim 5 , wherein a first width of the etch stop layer at the first height in the first direction is smaller than a second width of the etch stop layer at the second height in the first direction.
8. 8 . The semiconductor device of claim 1 , wherein the active pattern comprises a lower pattern, and a plurality of sheet patterns spaced apart from the lower pattern in the third direction, and wherein the gate electrode surrounds the plurality of sheet patterns.
9. 9 . The semiconductor device of claim 1 , wherein the upper surface of the source/drain pattern in the third direction is higher than a level of a lower surface of the plurality of gate structures.
10. 10 . The semiconductor device of claim 1 , wherein the second contact liner has a width that is increased as the second contact liner extends away from the upper surface of the source/drain pattern in the third direction.
11. 11 . The semiconductor device of claim 1 , further comprising a contact silicide layer between the source/drain pattern and the source/drain contact.
12. 12 . A semiconductor device comprising: an active pattern extended in a first direction; a plurality of gate structures comprising a gate electrode and a gate spacer, which are disposed to be spaced apart from each other in the first direction on the active pattern and extended in a second direction, and a gate capping layer on the gate electrode and the gate spacer; a source/drain pattern on the active pattern; an etch stop layer extended along a sidewall of the plurality of gate structures and an upper surface of the source/drain pattern; a source/drain contact on the source/drain pattern; and a contact liner structure extended along a sidewall of the source/drain contact on the etch stop layer, wherein the contact liner structure comprises a first contact liner, and a second contact liner extended along the first contact liner and disposed between the first contact liner and the source/drain contact, wherein the etch stop layer is in contact with a sidewall of the first contact liner at a first height in a third direction perpendicular to the first direction and the second direction, wherein an interlayer insulating layer is disposed between the etch stop layer and the sidewall of the first contact liner at a second height lower than the first height, and wherein the sidewall of the source/drain contact extends downwardly beyond a bottom portion of the first contact liner and a lower end portion of the second contact liner.
13. 13 . The semiconductor device of claim 12 , wherein the first height in the third direction is greater than a height from a lower surface of the plurality of gate structures to a point where the gate capping layer and the etch stop layer meet.
14. 14 . The semiconductor device of claim 12 , wherein the etch stop layer at the first height is in contact with the gate capping layer, and the etch stop layer at the second height is in contact with the gate spacer.
15. 15 . The semiconductor device of claim 12 , wherein a first width of the etch stop layer at the first height in the first direction is smaller than a second width of the etch stop layer at the second height in the first direction.
16. 16 . The semiconductor device of claim 12 , wherein the second contact liner comprises a material having a dielectric constant lower than that of the first contact liner.
17. 17 . The semiconductor device of claim 12 , wherein the second contact liner comprises carbon, and a concentration of carbon contained in the second contact liner increases as the second contact liner extends away from the upper surface of the source/drain pattern in the third direction.
18. 18 . The semiconductor device of claim 12 , wherein the first contact liner comprises: a first bottom portion that is in contact with a bottom surface of the etch stop layer; and a first vertical portion protruded from the first bottom portion and extended in the third direction.
19. 19 . The semiconductor device of claim 12 , wherein a width of the second contact liner is increased as the second contact liner extends away from the upper surface of the source/drain pattern.
20. 20 . A semiconductor device comprising: an active pattern comprising a lower pattern extended in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction; a plurality of gate structures comprising a gate electrode and a gate spacer, which are disposed to be spaced apart from each other in the first direction on the active pattern and extended in a third direction crossing the first direction and the second direction; a source/drain pattern on the active pattern; a source/drain contact on the source/drain pattern; an etch stop layer extended along a sidewall of the plurality of gate structures and an upper surface of the source/drain pattern; and a contact liner structure extended along a sidewall of the source/drain contact on the etch stop layer, wherein the contact liner structure comprises a first contact liner and a second contact liner on the first contact liner, wherein the first contact liner comprises a first bottom portion, and a first vertical portion protruded from the first bottom portion and extended in the second direction, wherein the etch stop layer is in contact with the first vertical portion at a first height in the second direction, wherein an interlayer insulating layer is disposed between the etch stop layer and the first vertical portion at a second height lower than the first height, and wherein the sidewall of the source/drain contact extends downwardly beyond the first bottom portion of the first contact liner and a lower end portion of the second contact liner.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0068725, filed on Jun. 7, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND 1. Field The disclosure relates to a semiconductor device. 2. Description of Related Art A scaling technique for increasing a density of a semiconductor device includes a multi-gate transistor for forming a multi-channel active pattern (or silicon body) of a fin or nano-wire shape on a substrate, and forming a gate on a surface of the multi-channel active pattern. As a pitch size of a semiconductor device is reduced, there is a need for reducing capacitance and ensuring electrical stability between contacts in the semiconductor device. SUMMARY Various embodiments of the present disclosure provide for a semiconductor device capable of improving device performance and reliability. According to an aspect of the present disclosure, a semiconductor device includes an active pattern extended in a first direction, a plurality of gate structures including a gate electrode and a gate spacer, which are disposed to be spaced apart from each other in the first direction on the active pattern and extended in a second direction, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a contact liner structure extended along a sidewall of the source/drain contact, being in contact with the sidewall of the source/drain contact. The contact liner structure includes a first contact liner and a second contact liner on the first contact liner. The first contact liner includes a first bottom portion, and a first vertical portion protruded from the first bottom portion and extended in a third direction. A lower surface of the contact liner structure is higher than an upper surface of the source/drain pattern. According to an aspect of the present disclosure, a semiconductor device includes an active pattern extended in a first direction, a plurality of gate structures including a gate electrode and a gate spacer, which are disposed to be spaced apart from each other in the first direction on the active pattern and extended in a second direction, and a gate capping layer on the gate electrode and the gate spacer, a source/drain pattern on the active pattern, an etch stop layer extended along a sidewall of the plurality of gate structures and an upper surface of the source/drain pattern, a source/drain contact on the source/drain pattern, and a contact liner structure extended along a sidewall of the source/drain contact on the etch stop layer. The contact liner structure includes a first contact liner, and a second contact liner extended along the first contact liner and disposed between the first contact liner and the source/drain contact. The etch stop layer is in contact with a sidewall of the first contact liner at a first height in a third direction perpendicular to the first direction and the second direction. An interlayer insulating layer is disposed between the etch stop layer and the sidewall of the first contact liner at a second height lower than the first height. According to an aspect of the present disclosure, a semiconductor device includes an active pattern including a lower pattern extended in a first direction and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction, a plurality of gate structures including a gate electrode and a gate spacer, which are disposed to be spaced apart from each other in the first direction on the active pattern and extended in a third direction crossing the first direction and the second direction, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, an etch stop layer extended along a sidewall of the plurality of gate structures and an upper surface of the source/drain pattern, and a contact liner structure extended along a sidewall of the source/drain contact on the etch stop layer. The contact liner structure includes a first contact liner and a second contact liner on the first contact liner. The first contact liner includes a first bottom portion, and a first vertical portion protruded from the first bottom portion and extended in the second direction. The etch stop layer is in contact with the first vertical portion at a first height in the second direction. An interlayer insulating layer is disposed between the etch stop layer and the first vertical portion at a second height lower than the first height. The aspects of the present disclosure are not limited to those mentioned above and additional aspects of the present disclosure, which are not mentioned herein, will be clearly understood by those skilled in the art from the following description. BRIEF DESCRIPTION OF DRAWINGS The above and other aspects an