US-12622018-B2 - Multi-layered or graded semiconductor region in thin film transistor (TFT) structures

US12622018B2US 12622018 B2US12622018 B2US 12622018B2US-12622018-B2

Abstract

Techniques for forming thin film transistors (TFTs) having multilayer and/or concentration gradient semiconductor regions. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, and a semiconductor region on the gate dielectric. In some cases, the semiconductor region includes a plurality of compositionally different material layers, at least two layers of the different material layers each being a semiconductor layer. In some other cases, the semiconductor region includes a single layer having a material concentration gradient extending from a bottom surface of the single layer (adjacent to the gate dielectric) to a top surface of the single layer. The integrated circuit further includes first and second conductive contacts that each contact a respective portion of the semiconductor region. One example application of the techniques is with respect to forming backend (within the interconnect region) memory structures configured with multilayer and/or concentration gradient TFTs.

Inventors

Timothy JEN
Shailesh Kumar Madisetti
Xiaojun Weng
Prem Chanani
Cheng Tan
Brian Wadsworth
Andre Baran
James Pellegren
Christopher J. Wiegand
Van H. Le
Abhishek Anil Sharma

Assignees

INTEL CORPORATION

Dates

Publication Date: 20260505
Application Date: 20220512

Claims (20)

1 . An integrated circuit, comprising: a gate electrode; a gate dielectric on the gate electrode; a semiconductor region on the gate dielectric, wherein the semiconductor region includes one of (1) a plurality of compositionally different material layers comprising a first semiconductor layer on the gate dielectric, a second semiconductor layer over the first semiconductor layer, and a third layer over the second semiconductor layer, or (2) a single layer having a material concentration gradient extending from a bottom surface of the single layer adjacent to the gate dielectric to a top surface of the single layer; and first and second conductive contacts that land within the first, second or third layer, or on a top surface of the first, second or third layer or that each contact a respective portion of the single layer.
2 . The integrated circuit of claim 1 , wherein the semiconductor region includes the single layer having the material concentration gradient and comprises an increasing gradient of indium from the bottom surface of the single layer to the top surface of the single layer, and a decreasing gradient of gallium from the bottom surface of the single layer to the top surface of the single layer.
3 . The integrated circuit of claim 1 , wherein the semiconductor region includes the single layer having the material concentration gradient and comprises one or both of (1) an increasing gradient of dopant from the bottom surface of the single layer to the top surface of the single layer, and (2) a decreasing gradient of a counter-dopant from the bottom surface of the single layer to the top surface of the single layer.
4 . The integrated circuit of claim 1 , wherein the semiconductor region includes the single layer having the material concentration gradient and comprises indium, gallium, zinc, and oxygen.
5 . The integrated circuit of claim 1 , wherein the first and second conductive contacts extend through a thickness of the third layer and land on a top surface of the second semiconductor layer.
6 . The integrated circuit of claim 1 , wherein: the first semiconductor layer comprises a semiconductor material having a first gallium concentration, the second semiconductor layer comprises a semiconductor material having a second gallium concentration lower than the first gallium concentration, and the third layer comprises a semiconductor material having a third gallium concentration lower than the second gallium concentration.
7 . A printed circuit board comprising the integrated circuit of claim 1 .
8 . The integrated circuit of claim 1 , wherein the first semiconductor layer has a lower conductivity compared to the second semiconductor layer and the third layer.
9 . The integrated circuit of claim 1 , wherein the first and second conductive contacts each comprise a barrier layer and a metal fill, wherein the barrier layer has a semiconductor material with a same composition as the semiconductor material of at least one of the layers of the semiconductor region.
10 . An integrated circuit, comprising: a plurality of semiconductor devices; an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers; a thin film transistor (TFT) structure across one or more interconnect layers of the plurality of stacked interconnect layers, the TFT structure comprising a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, wherein the semiconductor region includes a first semiconductor layer on the gate dielectric, a second semiconductor layer over the first semiconductor layer, and a third layer over the second semiconductor layer, and first and second conductive contacts that extend through a thickness of the third layer and land on a top surface of the second semiconductor layer.
11 . A printed circuit board comprising the integrated circuit of claim 10 .
12 . The integrated circuit of claim 10 , wherein the first semiconductor layer has a lower conductivity compared to the second semiconductor layer and the third layer.
13 . The integrated circuit of claim 10 , wherein the first and second conductive contacts each comprise a barrier layer and a metal fill, wherein the barrier layer has a semiconductor material with a same composition as the semiconductor material of at least one of the layers of the semiconductor region.
14 . The integrated circuit of claim 10 , wherein the first semiconductor layer comprises a semiconductor material having a first gallium concentration, the second semiconductor layer comprises a semiconductor material having a second gallium concentration lower than the first gallium concentration, and the third layer comprises a semiconductor material having a third gallium concentration lower than the second gallium concentration.
15 . The integrated circuit of claim 14 , wherein the semiconductor material of each of the first, second, and third layers comprises indium, gallium, zinc, and oxygen.
16 . An integrated circuit, comprising: a plurality of semiconductor devices; an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers; a thin film transistor (TFT) structure across one or more interconnect layers of the plurality of stacked interconnect layers, the TFT structure comprising a gate electrode, a gate dielectric on the gate electrode, a semiconductor layer on the gate dielectric, wherein the semiconductor layer has a material concentration gradient extending from a bottom surface of the semiconductor layer adjacent to the gate dielectric to a top surface of the semiconductor layer, and first and second conductive contacts that each contact a respective portion of the semiconductor layer.
17 . A printed circuit board comprising the integrated circuit of claim 16 .
18 . The integrated circuit of claim 16 , wherein the semiconductor layer comprises indium, gallium, zinc, and oxygen.
19 . The integrated circuit of claim 18 , wherein the gallium has the concentration gradient within the semiconductor layer.
20 . The integrated circuit of claim 19 , wherein the semiconductor layer has a maximum gallium concentration at the bottom surface of the semiconductor layer and a minimum gallium concentration at the top surface of the semiconductor layer.

Description

FIELD OF THE DISCLOSURE The present disclosure relates to integrated circuits, and more particularly, to multilayer and/or or concentration gradient semiconductor regions in thin film transistor structures. BACKGROUND As integrated circuits continue to scale downward in size, a number of challenges arise. For instance, as transistor area decreases, so too do the dimensions for interconnects made to the various transistor structures, such as gate structures, drain regions, and source regions. Structures formed in such interconnect layers may be highly affected by process variations leading to subsequent variations in device performance or low yield of workable devices. Accordingly, there remain a number of non-trivial challenges with respect to the formation of backend structures in integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a cross-sectional view that illustrates an example portion of an integrated circuit configured with an interconnect region having tiers of memory structures that include thin film transistor structures having multilayer semiconductor regions, in accordance with an embodiment of the present disclosure. FIG. 1B is a plan view of an array of memory structures and generally illustrates structures formed across different interconnect layers, in accordance with an embodiment of the present disclosure. FIGS. 2A-2J″ are cross-sectional views that collectively illustrate an example process for forming a thin film transistor (TFT) based memory structure having a multi-layer and/or concentration gradient semiconductor region, in accordance with an embodiment of the present disclosure. FIG. 3 illustrates a cross-section view of a chip package containing one or more semiconductor dies, in accordance with some embodiments of the present disclosure. FIG. 4 is a flowchart of a method for forming a TFT structure having a multi-layer and/or concentration gradient semiconductor region, in accordance with an embodiment of the present disclosure. FIG. 5 illustrates a computing system including one or more integrated circuits, as variously described herein, in accordance with an embodiment of the present disclosure. Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of this disclosure. As will be further appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For instance, while some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and/or rounded corners), and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used. DETAILED DESCRIPTION Techniques are provided herein for forming thin film transistor structures having multilayer and/or concentration gradient semiconductor regions. While the techniques can be used in any number of applications, they are particularly useful in forming backend (e.g., within the interconnect region) memory structures configured with TFTs having a multi-layer and/or concentration gradient semiconductor region (sometimes called a channel region or channel layer or channel structure). Such a semiconductor region can be used, for instance, to reduce contact resistance and increase thermal stability. According to an example, a given memory structure generally includes memory cells, with each memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. In such cases, the TFT structure allows the capacitor to be accessed during write operations (to store a memory bit) and read operations (to read a previously-stored bit). According to some such embodiments, the memory structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer semiconductor region that includes at least two or more different semiconductor layers and/or concentration gradient. The different layers (or concentration gradient(s) within a given layer, as the case may be) allow for different etch rates through each layer to controllably form contact recesses, according to some examples. Furthermore, the different layers and/or concentration gradient(s) can be tuned for higher mobility closer to the gate dielectric and for blocking leakage current. Numerous variations and embodiments will be apparent in light of this disclosure. General Overview As pre