US-12622019-B2 - Field effect transistor and method for manufacturing same, and display panel

US12622019B2US 12622019 B2US12622019 B2US 12622019B2US-12622019-B2

Abstract

The present disclosure provides a field effect transistor and a method for manufacturing the same, and a display panel, relating to the field of display technologies. The field effect transistor includes a substrate, an active layer, a source, a drain, a first insulating layer and an oxygenating layer. An orthographic projection of the oxygenating layer on the substrate is overlapped with an orthographic projection of a target region of the active layer on the substrate. Therefore, when the oxygenating layer is prepared, oxygen elements in the process environment can diffuse to the target region of the active layer, to oxygenate the active layer. In this way, oxygen vacancies in the active layer can be reduced, and the uniformity and stability of the active layer is improved, thereby further improving the performance of the field effect transistor.

Inventors

Dongfang Wang
Jie Huang

Assignees

BOE TECHNOLOGY GROUP CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20211126

Claims (16)

1 . A field effect transistor, comprising: a substrate; an active layer disposed on a side of the substrate; a source and a drain disposed on a side of the active layer away from the substrate; a first insulating layer disposed on a side, away from the substrate, of the source and the drain, wherein the first insulating layer is provided with an opening region, the active layer comprises a target region in the opening region, and the target region is between the source and the drain; and an oxygenating layer disposed on a side of the first insulating layer away from the substrate, wherein an orthographic projection of the oxygenating layer on the substrate is overlapped with an orthographic projection of the target region of the active layer on the substrate, wherein the field effect transistor further comprises: a first gate insulating layer disposed between the oxygenating layer and the first insulating layer, wherein an orthographic projection of the first gate insulating layer on the substrate is overlapped with an orthographic projection of opening region on the substrate; and a first gate disposed on a side of the first gate insulating layer away from the substrate, wherein the oxygenating layer and the first gate insulating layer are an integral structure.
2 . The field effect transistor according to claim 1 , wherein the orthographic projection of the target region of the active layer on the substrate is within the orthographic projection of the oxygenating layer on the substrate.
3 . The field effect transistor according to claim 1 , wherein a material of the oxygenating layer comprises: at least one of indium gallium zinc oxide, indium tin oxide, indium gallium tin oxide, indium zinc oxide, aluminum oxide, copper oxide, silicon oxide, hafnium oxide, zirconium oxide, and tantalum oxide.
4 . The field effect transistor according to claim 1 , wherein a material of the first gate insulating layer comprises at least one of silicon oxide and aluminum oxide.
5 . The field effect transistor according to claim 4 , wherein the material of the oxygenating layer and the material of the first gate insulating layer are both silicon oxide, and a ratio of an etching rate of the oxygenating layer to an etching rate of the first gate insulating layer ranges from 1.2 to 1.5 when the oxygenating layer and the first gate insulating layer are etched with a hydrogen fluoride solution.
6 . The field effect transistor according to claim 4 , wherein the material of the oxygenating layer and the material of the first gate insulating layer are both aluminum oxide, and a ratio of an etching rate of the oxygenating layer to an etching rate of the first gate insulating layer ranges from 1 to 1.6 when the oxygenating layer and the first gate insulating layer are etched with a hydrogen fluoride solution.
7 . The field effect transistor according to claim 1 , wherein a thickness of the oxygenating layer ranges from 5 nm to 50 nm.
8 . A method for manufacturing a field effect transistor, comprising: forming an active layer and a source-drain electrode in sequence on a substrate; forming a first insulating layer on the substrate on which the source-drain electrode is formed, wherein the first insulating layer is provided an opening region, and the active layer comprises a target region in the opening region; and forming an oxygenating layer on the substrate on which the first insulating layer is formed, wherein an orthographic projection of the oxygenating layer on the substrate is overlapped with an orthographic projection of the target region of the active layer on the substrate, wherein the field effect transistor comprises: a substrate; an active layer disposed on a side of the substrate; a source and a drain disposed on a side of the active layer away from the substrate; a first insulating layer disposed on a side, away from the substrate, of the source and the drain, wherein the first insulating layer is provided with an opening region, the active layer comprises a target region in the opening region, and the target region is between the source and the drain; and an oxygenating layer disposed on a side of the first insulating layer away from the substrate, wherein an orthographic projection of the oxygenating layer on the substrate is overlapped with an orthographic projection of the target region of the active layer on the substrate, wherein the field effect transistor further comprises: a first gate insulating layer disposed between the oxygenating layer and the first insulating layer, wherein an orthographic projection of the first gate insulating layer on the substrate is overlapped with an orthographic projection of opening region on the substrate; and a first gate disposed on a side of the first gate insulating layer away from the substrate, wherein the oxygenating layer and the first gate insulating layer are an integral structure.
9 . The method according to claim 8 , wherein forming the oxygenating layer on the substrate on which the first insulating layer is formed comprises: in an environment with an oxygen concentration greater than or equal to 20%, forming the oxygenating layer on the substrate on which the first insulating layer is formed by a preset process.
10 . The method according to claim 8 , wherein forming the oxygenating layer on the substrate on which the first insulating layer is formed comprises: in an environment with an oxygen concentration greater than or equal to 20%, forming the oxygenating layer on the substrate on which the first insulating layer is formed with an insulating material by a preset process, wherein the oxygenating layer is reused as a first gate insulating layer; and after forming the oxygenating layer on the substrate on which the first insulating layer is formed, the method further comprises: forming a first gate on the substrate on which the oxygenating layer is formed.
11 . The method according to claim 9 , wherein the preset process is a sputtering deposition process or an atomic layer deposition process.
12 . A display panel, comprising: a substrate, and a plurality of field effect transistors disposed on the substrate, and each of the field effect transistors comprises: a substrate; an active layer disposed on a side of the substrate; a source and a drain disposed on a side of the active layer away from the substrate; a first insulating layer disposed on a side, away from the substrate, of the source and the drain, wherein the first insulating layer is provided with an opening region, the active layer comprises a target region in the opening region, and the target region is between the source and the drain; and an oxygenating layer disposed on a side of the first insulating layer away from the substrate, wherein an orthographic projection of the oxygenating layer on the substrate is overlapped with an orthographic projection of the target region of the active layer on the substrate, wherein the field effect transistor further comprises: a first gate insulating layer disposed between the oxygenating layer and the first insulating layer, wherein an orthographic projection of the first gate insulating layer on the substrate is overlapped with an orthographic projection of opening region on the substrate; and a first gate disposed on a side of the first gate insulating layer away from the substrate, wherein the oxygenating layer and the first gate insulating layer are an integral structure.
13 . The display panel according to claim 12 , wherein the orthographic projection of the target region of the active layer on the substrate is within the orthographic projection of the oxygenating layer on the substrate.
14 . The display panel according to claim 12 , wherein a material of the oxygenating layer comprises: at least one of indium gallium zinc oxide, indium tin oxide, indium gallium tin oxide, indium zinc oxide, aluminum oxide, copper oxide, silicon oxide, hafnium oxide, zirconium oxide, and tantalum oxide.
15 . The display panel according to claim 12 , wherein a material of the first gate insulating layer comprises at least one of silicon oxide and aluminum oxide.
16 . The display panel according to claim 12 , wherein a thickness of the oxygenating layer ranges from 5 nm to 50 nm.

Description

CROSS-REFERENCE TO RELATED APPLICATION This present disclosure is a U.S. national stage of international application No. PCT/CN2021/133706, filed on Nov. 26, 2021, the disclosure of which is herein incorporated by reference in its entirety. TECHNICAL FIELD The present disclosure relates to the field of display technologies, and in particular, relates to a field effect transistor and a method for manufacturing the same, and a display panel. BACKGROUND Currently, indium gallium zinc oxide (IGZO) is widely used for preparing an active layer of a field effect transistor (FET) due to its high mobility, good uniformity, good transparency and the like. SUMMARY Embodiments of the present disclosure provide a field effect transistor and a method for manufacturing the same, and a display panel. The technical solutions are as follows. According to some embodiments of the present disclosure, a field effect transistor is provided. The field effect transistor includes: a substrate;an active layer disposed on a side of the substrate;a source and a drain disposed on a side of the active layer away from the substrate;a first insulating layer disposed on a side, away from the substrate, of the source and the drain, wherein the first insulating layer is provided with an opening region, the active layer includes a target region in the opening region, and the target region is between the source and the drain;an oxygenating layer disposed on a side of the first insulating layer away from the substrate, wherein an orthographic projection of the oxygenating layer on the substrate is overlapped with an orthographic projection of the target region of the active layer on the substrate. In some embodiments, the orthographic projection of the target region of the active layer on the substrate is within the orthographic projection of the oxygenating layer on the substrate. In some embodiments, the field effect transistor further includes: a first gate insulating layer disposed between the oxygenating layer and the first insulating layer, wherein an orthographic projection of the first gate insulating layer on the substrate is overlapped with an orthographic projection of opening region on the substrate; anda first gate disposed on a side of the first gate insulating layer away from the substrate. In some embodiments, the oxygenating layer and the first gate insulating layer are an integral structure. In some embodiments, a material of the oxygenating layer includes: at least one of indium gallium zinc oxide, indium tin oxide, indium gallium tin oxide, indium zinc oxide, aluminum oxide, copper oxide, silicon oxide, hafnium oxide, zirconium oxide, and tantalum oxide. In some embodiments, a material of the first gate insulating layer includes at least one of silicon oxide and aluminum oxide. In some embodiments, the material of the oxygenating layer and the material of the first gate insulating layer are both silicon oxide, and a ratio of an etching rate of the oxygenating layer to an etching rate of the first gate insulating layer ranges from 1.2 to 1.5 when the oxygenating layer and the first gate insulating layer are etched with a hydrogen fluoride solution. In some embodiments, the material of the oxygenating layer and the material of the first gate insulating layer are both aluminum oxide, and a ratio of an etching rate of the oxygenating layer to an etching rate of the first gate insulating layer ranges from 1 to 1.6 when the oxygenating layer and the first gate insulating layer are etched with a hydrogen fluoride solution. In some embodiments, a thickness of the oxygenating layer ranges from 5 nm to 50 nm. According to some embodiments of the present disclosure, a method for manufacturing a field effect transistor is provided. The method includes: forming an active layer and a source-drain electrode in sequence on a substrate;forming a first insulating layer on the substrate on which the source-drain electrode is formed, wherein the first insulating layer is provided an opening region, and the active layer includes a target region in the opening region; andforming an oxygenating layer on the substrate on which the first insulating layer is formed, wherein an orthographic projection of the oxygenating layer on the substrate is overlapped with an orthographic projection of the target region of the active layer on the substrate. In some embodiments, forming the oxygenating layer on the substrate on which the first insulating layer is formed includes: in an environment with an oxygen concentration greater than or equal to 20%, forming the oxygenating layer on the substrate on which the first insulating layer is formed by a preset process. In some embodiments, forming the oxygenating layer on the substrate on which the first insulating layer is formed includes: in an environment with an oxygen concentration greater than or equal to 20%, forming the oxygenating layer on the substrate on which the first insulating layer is formed with an i