US-12622020-B2 - Silicon carbide MOSFET transistor device with improved characteristics and corresponding manufacturing process

US12622020B2US 12622020 B2US12622020 B2US 12622020B2US-12622020-B2

Abstract

A MOSFET transistor device includes a functional layer of silicon carbide, having a first conductivity type. Gate structures are formed on a top surface of the functional layer and each includes a dielectric region and an electrode region. Body wells having a second conductivity type are formed within the functional layer, and the body wells are separated from one another by surface-separation regions. Source regions having the first conductivity type are formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.

Inventors

Patrick FIORENZA
Fabrizio Roccaforte
Edoardo ZANETTI
Mario Giuseppe Saggio

Assignees

STMICROELECTRONICS S.R.L.

Dates

Publication Date: 20260505
Application Date: 20211222
Priority Date: 20201224

Claims (18)

1 . A MOSFET transistor device, comprising: a functional layer of silicon carbide, having a first conductivity type; gate structures formed on a top surface of said functional layer, each of the gate structures including a dielectric region and an electrode region; body wells having a second conductivity type, formed within said functional layer, the body wells separated from one another by surface-separation regions of said functional layer; source regions having said first conductivity type, the source regions formed within said body wells, laterally and partially underneath respective gate structures; and modified-doping regions, arranged in the surface-separation regions of said functional layer, underneath respective gate structures, said modified-doping regions having a modified concentration of dopant as compared to the concentration of the functional layer, wherein the modified-doping regions have said first conductivity type, with a net concentration of dopant reduced as compared to the concentration of the functional layer, between 5% and 50% of the concentration of dopant of the functional layer.
2 . The device according to claim 1 , wherein said modified-doping regions are arranged centrally with respect to the surface-separation regions, underneath the dielectric regions of the respective gate structures.
3 . The device according to claim 1 , wherein said modified-doping regions extend transversally throughout an entire width of the respective surface-separation regions, terminating at the body wells.
4 . The device according to claim 1 , wherein said modified-doping regions have a thickness, in a vertical direction, transverse to the top surface, that is between 10% and 50% of the thickness of the body wells.
5 . The device according to claim 1 , wherein said surface-separation regions are JFET regions of said MOSFET transistor device.
6 . The device according to claim 1 , wherein the modified doping regions include a stack of a respective top layer and a respective bottom layer underlying the top layer, wherein the bottom layer has a higher dopant concentration than the functional layer and the top layer has a lower dopant concentration with respect to the bottom layer.
7 . The device according to claim 6 , wherein the dopant concentration of the bottom layer is between 1.5 and 50 times the dopant concentration of the functional layer, and the dopant concentration of the top layer is between 0.1 and 0.5 times the dopant concentration of the bottom layer.
8 . The device according to claim 6 , wherein a depth level of the bottom layer with respect to the top surface of the functional layer is between 0.5 and 1.2 times a respective depth level of the body wells, and a thickness of the top layer is between 0.1 and 0.5 times a respective thickness of the bottom layer.
9 . The device according to claim 6 , wherein a width of the top layer and a respective width of the bottom layer are, independently from each other, less than or equal to a respective width of the surface-separation regions.
10 . A process for manufacturing a MOSFET transistor device, comprising: forming a functional layer of silicon carbide, having a first conductivity type; forming gate structures on a top surface of said functional layer, each of the gate structures including a dielectric region and an electrode region; forming body wells having a second conductivity type, within said functional layer, the body wells separated from one another by surface-separation regions of said functional layer; forming source regions having said first conductivity type, within said body wells, laterally and partially underneath respective gate structures; and forming modified-doping regions, arranged in the surface-separation regions of said functional layer, underneath respective gate structures, said modified-doping regions having a modified concentration of dopant as compared to the concentration of the functional layer, wherein forming said modified-doping regions comprises performing a localized implantation in the surface-separation regions, aimed at partial deactivation or enrichment of the doping of the first conductivity type of the functional layer.
11 . The process according to claim 10 , wherein performing a localized implantation comprises performing an implantation with atoms of the second conductivity type in the surface-separation regions, said implantation providing a counter-doping and therefore a partial deactivation of the doping of the functional layer, thus leading to formation of the modified-doping regions with reduced net doping concentration.
12 . The process according to claim 10 , wherein performing a localized implantation comprises performing an implantation in the surface-separation regions of silicon atoms, designed to damage, and thus deactivate, the doping in the surface-separation regions, thus leading to the formation of the modified-doping regions with reduced net doping concentration.
13 . The process according to claim 10 , wherein said modified-doping regions are arranged centrally with respect to the surface-separation regions, underneath the dielectric regions of the respective gate structures.
14 . The process according to claim 10 , wherein said modified-doping regions extend transversally throughout an entire width of the respective surface-separation regions, terminating at the body wells.
15 . The process according to claim 10 , wherein forming said functional layer comprises forming, on a substrate, a first epitaxial layer having said first conductivity type and a desired doping concentration for said functional layer, and wherein forming said modified-doping regions comprises forming a second epitaxial layer on the first epitaxial layer, having said modified dopant concentration.
16 . The process according to claim 15 , wherein forming said body wells and forming said source regions comprises performing respective implantations in a surface portion of said functional layer, adjusting a density of surface doping of implanted regions so as to take into account the doping already present in the second epitaxial layer.
17 . A MOSFET transistor device, comprising: a functional layer of silicon carbide, having a first conductivity type; a first gate structure and a second gate structure spaced apart from each other on the functional layer; a body well region of a second conductivity type in the functional layer extending in a U shape from the first gate structure to the second gate structure; a source region of the first conductivity type in the functional layer above a middle portion of the body well region and below both the first gate structure and the second gate structure; a first modified doping region of the first conductivity type in the functional layer below the first gate structure and spaced apart from the body well region and the source region and having a different doping concentration than the functional layer; and a second modified doping region of the first conductivity type in the functional layer below the second gate structure and spaced apart from the body well region and the source region and having a different doping concentration than the functional layer.
18 . The device according to claim 17 , wherein the first and second modified-doping regions are arranged centrally below the first and second gate structures, respectively.

Description

BACKGROUND Technical Field The present disclosure relates to a silicon carbide MOSFET transistor device with improved characteristics and to a corresponding manufacturing process. Description of the Related Art Electronic semiconductor devices are known, in particular MOSFET transistors (Metal-Oxide-Semiconductor Field-Effect Transistors), for example, for electronic power applications, which are made starting from a silicon carbide substrate. The above devices prove advantageous thanks to the favorable chemico-physical properties of silicon carbide. For instance, silicon carbide generally has a wider bandgap than silicon, which is commonly used in electronic devices. Consequently, even with relatively small thicknesses, silicon carbide has a higher breakdown voltage than silicon and may thus be advantageously used in high-voltage, high-power and high-temperature applications. In particular, thanks to its crystalline quality and to its large-scale availability, silicon carbide with hexagonal polytype (4H-SiC) can be used for electronic power applications. Manufacturing of a silicon carbide semiconductor device is, however, affected by some problems. For instance, problems of crystallographic quality of silicon carbide may represent an obstacle to obtaining a high production yield, which may in general prove lower than those of similar devices made starting from silicon, consequently causing an increase in the production costs. In particular, it has been shown that reliability problems are linked to high electrical fields developing at the interfaces between silicon oxide (SiO2) and silicon carbide (4H-SiC). FIG. 1 shows a portion of a basic or elementary structure (a so-called cell), of a MOSFET device of a vertical type, in particular an N-channel VDMOS (Vertical Double-Diffused Metal Oxide Semiconductor) device, for power applications, designated by 1 and comprising: a substrate of semiconductor material (in particular, silicon carbide 4H-SiC), which is heavily doped (for example, with N+-type doping, with high doping concentration, for instance higher than 1018 atoms/cm3), not illustrated herein, and an epitaxial layer (referred to as drift layer) 2, also made of silicon carbide, having the same conductivity type as, and overlying, the substrate, with a lower dopant concentration (N−). The substrate operates as drain for the MOSFET device 1, and the epitaxial layer 2 constitutes a surface extension thereof defining a top surface 2a. Each cell of the MOSFET device 1 comprises a body well 4 having a conductivity opposite to that of the epitaxial layer 2 (in the example, of a P type), and a source region 5, arranged within the body well 4 at the top surface 2a, having the same conductivity type as the substrate 2 and a high dopant concentration (N+). The surface portion of the epitaxial layer 2, arranged at the top surface 2a and interposed between adjacent body wells 4, is commonly referred to as JFET region. The device 1 further comprises a gate structure 6, constituted by a gate dielectric region 7, for example, of silicon oxide, formed on the JFET region and partially overlapping the body well 4 and the source region 5; and a gate electrode 8 provided on the gate dielectric region 7. A dielectric material region 9, for example, of field oxide, overlies the gate electrode 8; an electrical-contact region 11 is defined through this dielectric material region 9, designed to contact a surface portion of the source region 5. A source metallization 12 is arranged in contact with the aforesaid electrical-contact region 11; moreover, in a way not illustrated, a drain metallization contacts the substrate from the back and gate metallizations, provided within contact openings provided through the dielectric material region 9, contact the gate electrodes 8. The channel of each cell of the MOSFET device 1 is formed in the portion of the corresponding body well 4 set directly underneath the gate electrode 8, and is delimited by the junction between the source region 5 and the body well 4 on one side, and by the junction between the same body well 4 and the JFET region, on the other side. The gate electrode 8 is capacitively coupled to the channel to modulate the conductivity type thereof; in particular, application of an appropriate voltage to the gate electrode 8 allows to cause channel inversion and thus create a conductive path for the electrons between the source region 5 (first current-conduction region of the device) and the substrate (second current-conduction region of the device), through the channel and the drift layer. A problem afflicting silicon carbide MOSFET devices is linked to the increase in the electrical field on account of the possible crystallographic defects, with the electrical field that tends to increase in the insulating material, in particular in the gate dielectric region 7 at the central part of the JFET region, especially in reverse-biasing configuration. FIG. 2 shows the trend of the e