US-12622021-B2 - Semiconductor structure with conductive spacer in shallow trench isolation region

Abstract

A semiconductor structure includes a shallow trench isolation region disposed within a semiconductor substrate, and a conductive spacer disposed within the shallow trench isolation region.

Inventors

• Koichi Motoyama
• Ruilong Xie
• Kisik Choi
• Chih-Chao Yang

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260505

Application Date

20221010

Claims (20)

1. 1 . A semiconductor structure, comprising: a shallow trench isolation region disposed within a semiconductor substrate; a conductive spacer disposed within the shallow trench isolation region; and a backside power rail disposed on a bottom surface of the conductive spacer; wherein a bottom surface of the conductive spacer is coplanar with a bottom surface of the shallow trench isolation region.
2. 2 . The semiconductor structure of claim 1 , wherein conductive spacer is disposed on a liner layer in the shallow trench isolation region.
3. 3 . The semiconductor structure of claim 1 , wherein the conductive spacer is ruthenium.
4. 4 . The semiconductor structure of claim 1 , further comprising a via-to-backside power rail disposed on a top surface of the conductive spacer.
5. 5 . The semiconductor structure of claim 1 , wherein a top surface of the conductive spacer is coplanar with a top surface of the shallow trench isolation region.
6. 6 . A semiconductor structure, comprising: a plurality of shallow trench isolation regions disposed within a semiconductor substrate; a conductive spacer disposed within one of the plurality of shallow trench isolation regions; and a via-to-backside power rail disposed on a top surface of the conductive spacer; wherein the top surface of the conductive spacer is coplanar with a top surface of the one of the plurality of shallow trench isolation regions; and wherein the conductive spacer has a first width and the via-to-backside power rail has a second width less than the first width.
7. 7 . The semiconductor structure of claim 6 , further comprising a liner layer disposed on sidewalls of the conductive spacer.
8. 8 . The semiconductor structure of claim 6 , wherein a top surface of the conductive spacer is below a top surface of the one of the plurality of shallow trench isolation regions.
9. 9 . The semiconductor structure of claim 6 , further comprising a backside power rail connected to the via-to-backside power rail though the conductive spacer.
10. 10 . The semiconductor structure of claim 9 , wherein the backside power rail is disposed in an interlayer dielectric layer.
11. 11 . The semiconductor structure of claim 9 , further comprising a source/drain contact disposed on the via-to-backside power rail, the source/drain contact being connected to the backside power rail through the via-to-backside power rail.
12. 12 . The semiconductor structure of claim 6 , further comprising a gate structure, wherein the conductive spacer is located away from the gate structure.
13. 13 . The semiconductor structure of claim 6 , wherein the conductive spacer is ruthenium.
14. 14 . A semiconductor structure, comprising: a plurality of shallow trench isolation regions disposed within a semiconductor substrate; a conductive spacer disposed within one of the plurality of shallow trench isolation regions; a plurality of stacked nanosheet channel layers located above the semiconductor substrate and between respective shallow trench isolation regions; and a via-to-backside power rail disposed on a top surface of the conductive spacer; wherein the top surface of the conductive spacer is coplanar with a top surface of the one of the plurality of shallow trench isolation regions; and wherein the conductive spacer has a first width and the via-to-backside power rail has a second width less than the first width.
15. 15 . The semiconductor structure of claim 14 , further comprising: a source/drain region disposed on each of the plurality of stacked nanosheet channel layers; and a source/drain contact disposed on the source/drain region and connected to the via-to-backside power rail.
16. 16 . The semiconductor structure of claim 15 , further comprising: a backside power rail connected to the source/drain contact though the conductive spacer and the via-to-backside power rail.
17. 17 . The semiconductor structure of claim 16 , wherein the backside power rail is disposed on one side of the conductive spacer and the via-to-backside power rail is disposed on another side of the conductive spacer.
18. 18 . The semiconductor structure of claim 14 , further comprising a liner layer disposed on sidewalls of the conductive spacer.
19. 19 . The semiconductor structure of claim 17 , wherein a top surface of the conductive spacer is below a top surface of the one of the plurality of shallow trench isolation regions.
20. 20 . The semiconductor structure of claim 14 , wherein the conductive spacer is ruthenium.

Description

BACKGROUND A field-effect transistor (FET) is a transistor having a source, a gate, and a drain, and having action that depends on the flow of carriers (electrons or holes) along a channel that runs between the source and drain. Current through the channel between the source and drain may be controlled by a transverse electric field under the gate. FETs are widely used for switching, amplification, filtering, and other tasks. FETs include metal-oxide-semiconductor FETs (MOSFETs). Complementary MOS (CMOS) devices are widely used, where both n-type and p-type transistors (nFET and pFET) are used to form logic and other circuitry. Source and drain regions of a FET are typically formed by adding dopants to target regions of a semiconductor body on either side of a channel, with the gate being formed above the channel. The gate includes a gate dielectric over the channel and a gate conductor over the gate dielectric. The gate dielectric is an insulator material that prevents large leakage current from flowing into the channel when voltage is applied to the gate conductor while allowing applied gate voltage to produce a transverse electric field in the channel. SUMMARY Illustrative embodiments of the present application include techniques for use in semiconductor manufacture. In one illustrative embodiment, a semiconductor structure comprises a shallow trench isolation region disposed within a semiconductor substrate, and a conductive spacer disposed within the shallow trench isolation region. In another illustrative embodiment, a semiconductor structure comprises a plurality of shallow trench isolation regions disposed within a semiconductor substrate, a conductive spacer disposed within one of the plurality of shallow trench isolation regions, and a via-to-backside power rail disposed on a top surface of the conductive spacer. The conductive spacer has a first width and the via-to-backside power rail has a second width less than the first width. In yet another illustrative embodiment, a semiconductor structure comprises a plurality of shallow trench isolation regions disposed within a semiconductor substrate, a conductive spacer disposed within one of the plurality of shallow trench isolation regions, a plurality of stacked nanosheet channel layers located above the semiconductor substrate and between respective shallow trench isolation regions, and a via-to-backside power rail disposed on a top surface of the conductive spacer. The conductive spacer has a first width and the via-to-backside power rail has a second width less than the first width. Other embodiments will be described in the following detailed description of embodiments, which is to be read in conjunction with the accompanying figures. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts a cross sectional view illustrating a semiconductor structure for use at a first-intermediate fabrication stage, according to an illustrative embodiment. FIG. 2 depicts a side cross-sectional view of a semiconductor structure for use at a second-intermediate fabrication stage, according to an illustrative embodiment. FIG. 3 depicts a side cross-sectional view of a semiconductor structure for use at a third-intermediate fabrication stage, according to an illustrative embodiment. FIG. 4 depicts a side cross-sectional view of a semiconductor structure for use at a fourth-intermediate fabrication stage, according to an illustrative embodiment. FIG. 5 depicts a side cross-sectional view of a semiconductor structure for use at a fifth-intermediate fabrication stage, according to an illustrative embodiment. FIG. 6 depicts a side cross-sectional view of a semiconductor structure for use at a sixth-intermediate fabrication stage, according to an illustrative embodiment. FIG. 7 depicts a side cross-sectional view of a semiconductor structure for use at a seventh-intermediate fabrication stage, according to an illustrative embodiment. FIG. 8 depicts a side cross-sectional view of a semiconductor structure for use at an eighth-intermediate fabrication stage, according to an illustrative embodiment. FIG. 9 depicts a cross-sectional view of a semiconductor structure for use at a ninth-intermediate fabrication stage, according to an illustrative embodiment. FIG. 10A depicts a top view of a semiconductor structure for use at a tenth-intermediate fabrication stage, according to an illustrative embodiment. FIG. 10B depicts a cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis of FIG. 10A for use at the tenth-intermediate fabrication stage, according to an illustrative embodiment. FIG. 11 depicts a side cross-sectional view of a semiconductor structure for use at an eleventh-intermediate fabrication stage, according to an illustrative embodiment. FIG. 12 is a cross-sectional view illustrating the semiconductor structure at a twelfth-intermediate fabrication stage, according to an illustrative embodiment. FIG. 13 is a cross-sectional view illustrating the semi