US-12622022-B2 - Semiconductor device and method of manufacturing thereof

Abstract

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first spacer on a bit line, wherein the first spacer includes low-k material doped with carbon. An oxidation process is performed to the first spacer such that a surface portion of the first spacer is transformed to an oxide spacer. The first spacer has a remaining first spacer that is not oxidized by the oxidation process. Then, a second spacer is formed on the oxide spacer, wherein the second spacer includes nitride. The oxide spacer is removed to form a gap between the remaining first spacer and the second spacer. A cover layer is formed to cover the bit line, the remaining first spacer, and the second spacer such that an air gap is sealed by the cover layer, the remaining first spacer, and the second spacer.

Inventors

• Wei Yu Chen

Assignees

• NANYA TECHNOLOGY CORPORATION

Dates

Publication Date

20260505

Application Date

20230517

Claims (14)

1. 1 . A semiconductor device, comprising: a substrate; a bit line located on the substrate; a first spacer located on a sidewall of the bit line, wherein the first spacer comprises a carbon-doped low-k material; a second spacer located on the substrate and adjacent to the first spacer, wherein the second spacer comprises nitride; an air gap between the first spacer and the second spacer; wherein a bottom of the air gap exposes the substrate; a cover layer, covering the bit line, the first spacer, and the second spacer such that the air gap is sealed by the cover layer, the first spacer, and the second spacer; and a bit line spacer located on the sidewall of the bit line, wherein the bit line spacer is between the first spacer and the bit line.
2. 2 . The semiconductor device of claim 1 , wherein the bit line spacer comprises nitride.
3. 3 . The semiconductor device of claim 1 , wherein the bit line spacer and the second spacer both comprise silicon nitride (SiN).
4. 4 . The semiconductor device of claim 1 , wherein the first spacer comprises silicon carbide (SiC).
5. 5 . The semiconductor device of claim 1 , wherein a width of the air gap is in a range from about 3 nm to about 4 nm.
6. 6 . A method of manufacturing a semiconductor device, comprising: forming a bit line on a substrate; forming a first blanket layer over a top surface and a sidewall of the bit line, wherein the first blanket layer comprises low-k material doped with carbon; removing a portion of the first blanket layer on the top surface of the bit line to form a first spacer on the sidewall of the bit line; performing an oxidation process to the first spacer such that a surface portion of the first spacer is transformed to an oxide spacer, wherein the oxide spacer is oxidized by the oxidation process, and the first spacer has a remaining first spacer that is not oxidized by the oxidation process; forming a second blanket layer over the bit line, the first spacer, and the oxide spacer, wherein the second blanket layer comprises nitride; removing a portion of the second blanket layer on the top surface of the bit line to form a second spacer on the oxide spacer; removing the oxide spacer to form a gap between the remaining first spacer and the second spacer; and forming a cover layer to cover the bit line, the remaining first spacer, and the second spacer such that an air gap is sealed by the cover layer, the remaining first spacer, and the second spacer.
7. 7 . The method of claim 6 , wherein the first blanket layer comprises silicon carbide (SiC).
8. 8 . The method of claim 6 , wherein after the oxidation process, the oxide spacer comprises silicon oxycarbide (SiCO).
9. 9 . The method of claim 6 , wherein the oxide spacer is removed by a gas etching process.
10. 10 . The method of claim 6 , further comprising: forming a bit line spacer on the sidewall of the bit line before forming the first blanket layer.
11. 11 . The method of claim 10 , wherein the bit line spacer, the second spacer, and the cover layer comprise silicon nitride (SiN).
12. 12 . The method of claim 6 , wherein the oxidation process is a plasma ashing process.
13. 13 . The method of claim 12 , wherein the oxidation process is performed with O 2 /(H 2 +N 2 ) plasma.
14. 14 . The method of claim 12 , wherein an oxygen diffusion depth of the plasma ashing process in the first spacer is in a range from about 3 nm to about 4 nm.

Description

BACKGROUND Field of Invention The present invention relates to semiconductor device and method of manufacturing thereof. More particularly, the present invention relates to the process of creating airgaps. Field of Invention With high integration of the semiconductor device, a distance between the conductive structures has decreased. For example, as the critical dimension shrink, when performing etching process to create airgaps, if the etching selectivity is not good, the process may lead to leakage or parasitic capacitance fail. Also, it would be a huge challenge to improve etching selectivity in a highly integrated semiconductor device. Therefore, how to form a structurally complete air gap between elements to effectively reduce the parasitic capacitance of the device is an important development item for semiconductor devices. SUMMARY In accordance with an aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a substrate and a bit line located on the substrate. A first spacer located on a sidewall of the bit line, wherein the first spacer includes a low-k material doped with carbon. A second spacer located on the substrate and adjacent to the first spacer, wherein the second spacer includes nitride. An air gap between the first spacer and the second spacer; wherein a bottom of the air gap exposes the substrate. A cover layer, covering the bit line, the first spacer, and the second spacer such that the air gap is sealed by the cover layer, the first spacer, and the second spacer. According to some embodiments of the present disclosure, the semiconductor device includes a bit line spacer located on the sidewall of the bit line, wherein the bit line spacer is between the first spacer and the bit line. According to some embodiments of the present disclosure, wherein the bit line spacer includes nitride. According to some embodiments of the present disclosure, wherein the bit line spacer and the second spacer both include silicon nitride (SiN). According to some embodiments of the present disclosure, wherein the first spacer includes silicon carbide (SiC). According to some embodiments of the present disclosure, wherein a width of the air gap is in a range from about 3 nm to about 4 nm. In accordance with an aspect of the present disclosure, a method of manufacturing a semiconductor device is provided. The method includes forming a bit line on a substrate. A first blanket layer is formed over a top surface and a sidewall of the bit line, wherein the first blanket layer includes low-k material doped with carbon. A portion of the first blanket layer on the top surface of the bit line is removed to form a first spacer on the sidewall of the bit line. An oxidation process is performed to the first spacer such that a surface portion of the first spacer is transformed to an oxide spacer, wherein the oxide spacer is oxidized by the oxidation process, and the first spacer has a remaining first spacer that is not oxidized by the oxidation process. A second blanket layer is formed over the bit line, the first spacer, and the oxide spacer, wherein the second blanket layer includes nitride. A portion of the second blanket layer on the top surface of the bit line is removed to form a second spacer on the oxide spacer. The oxide spacer is removed to form a gap between the remaining first spacer and the second spacer. A cover layer is formed to cover the bit line, the remaining first spacer, and the second spacer such that an air gap is sealed by the cover layer, the remaining first spacer, and the second spacer. According to some embodiments of the present disclosure, wherein the first blanket layer includes silicon carbide (SiC). According to some embodiments of the present disclosure, wherein after the oxidation process, the oxide spacer includes silicon oxycarbide (SiCO). According to some embodiments of the present disclosure, wherein the oxide spacer is removed by a gas etching process. According to some embodiments of the present disclosure, the method includes forming a bit line spacer on the sidewall of the bit line before forming the first blanket layer. According to some embodiments of the present disclosure, wherein the bit line spacer, the second spacer, and the cover layer include silicon nitride (SiN). According to some embodiments of the present disclosure, wherein the oxidation process is a plasma ashing process. According to some embodiments of the present disclosure, wherein the oxidation process is performed with O2/(H2+N2) plasma. According to some embodiments of the present disclosure, wherein an oxygen diffusion depth of the plasma ashing process in the first spacer is in a range from about 3 nm to about 4 nm. It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS The inventio