US-12622024-B2 - Semiconductor memory structure with L-shaped channel and method for manufacturing the same

Abstract

The semiconductor structure comprises: semiconductor channels, first gate structures, second gate structures and bit lines. Each semiconductor channel extends in a third direction and has an L-shaped cross-section in a plane perpendicular to the third direction, each of the semiconductor channels comprises a first L-shaped sidewall and a second L-shaped sidewall which are opposite to each other and extend in the third direction, the first L-shaped sidewall comprises a first face extending in a first direction and a second face extending in a second direction. Each first gate structure is in contact with the first face. Each second gate structures is in contact with the second face, each first gate structure is in contact with the respective second gate structure. The bit lines extend in the second direction and are located on a side of each of the semiconductor channels in the third direction.

Inventors

• Yi Tang

Assignees

• CHANGXIN MEMORY TECHNOLOGIES, INC.

Dates

Publication Date

20260505

Application Date

20231116

Priority Date

20221101

Claims (20)

1. 1 . A semiconductor structure, comprising: semiconductor channels extending in a third direction, each of the semiconductor channels has an L-shaped cross-section in a plane perpendicular to the third direction, each of the semiconductor channels comprises a first L-shaped sidewall and a second L-shaped sidewall which are opposite to each other and extend in the third direction, the first L-shaped sidewall comprises a first face extending in a first direction and a second face extending in a second direction; first gate structures, each of the first gate structures is in contact with the first face; second gate structures, each of the second gate structures is in contact with the second face, each of the first gate structures is in contact with a respective one of the second gate structures, and forms a combined structure together with the respective one of the second gate structures, the combined structure has an L-shaped cross-section in the plane perpendicular to the third direction; and bit lines extending in the second direction and located on a side of each of the semiconductor channels in the third direction; wherein the first direction, the second direction and the third direction intersect with each other.
2. 2 . The semiconductor structure according to claim 1 , wherein the semiconductor channels are arranged at intervals in the first direction, and adjacent semiconductor channels are arranged axisymmetrically.
3. 3 . The semiconductor structure according to claim 2 , wherein each of the first gate structures and each of the second gate structures are in a one-to-one correspondence with the semiconductor channels; the semiconductor structure further comprises: third gate structures, each of the third gate structures is in contact with ends of two adjacent second gate structures in the first direction, which are away from the respective first gate structure; and fourth gate structures, each of the fourth gate structures is in contact with ends of two adjacent first gate structures in the first direction, which are away from the respective second gate structure; wherein each of gate structures is formed by at least one of the first gate structures, at least one of the second gate structures, at least one of the third gate structures and at least one of the fourth gate structures.
4. 4 . The semiconductor structure according to claim 2 , wherein for every three adjacent semiconductor channels in the first direction, a neighboring pair among the three adjacent semiconductor channels is in contact with a same second gate structure, and another neighboring pair among the three adjacent semiconductor channels is in contact with a same first gate structure, the first gate structures and the second gate structures are alternately arranged in the first direction; and each of gate structures is formed by at least one of first gate structures and at least one of the second gate structures.
5. 5 . The semiconductor structure according to claim 1 , wherein the semiconductor channels are arranged at intervals in the first direction, and only one first face is provided between two adjacent second faces in the first direction; the first gate structures and the second gate structures are in a one-to-one correspondence with the semiconductor channels; each of the second gate structures is in contact with two adjacent first gate structures in the first direction; and each of gate structures is formed by at least one of the first gate structures and at least one of the second gate structures.
6. 6 . The semiconductor structure according to claim 3 , wherein the semiconductor channels are arranged at intervals in the second direction; the semiconductor channels arranged at intervals in the second direction are in a one-to-one correspondence with the gate structures; and spacings are provided between adjacent gate structures in the second direction.
7. 7 . The semiconductor structure according to claim 6 , wherein adjacent semiconductor channels in the second direction are arranged centrosymmetrically or axisymmetrically; each of the bit lines is contact with the semiconductor channels arranged at intervals in the second direction.
8. 8 . The semiconductor structure according to claim 6 , wherein adjacent semiconductor channels in the second direction are arranged centrosymmetrically; every two adjacent semiconductor channels in the second direction define a reference structure; two second faces of the reference structure are located in the spacing between two first faces; the semiconductor structure further comprises: first isolation layers in contact with both of two second L-shaped sidewalls in the reference structure; and second isolation layers located between adjacent first isolation layers in the first direction; the first isolation layers are in contact with the second isolation layers, and the first isolation layers and the second isolation layers are alternately arranged in the first direction.
9. 9 . The semiconductor structure according to claim 8 , wherein a length of each one of the first isolation layers in the second direction is a first length; a length of each one of the second isolation layers in the second direction is a second length; and a ratio of the second length to the first length ranges from ½ to ⅔.
10. 10 . The semiconductor structure according to claim 3 , wherein each of the gate structures comprises a gate dielectric layer and a gate; the gate dielectric layer is disposed on the first face and the second face; the gate dielectric layer is in a one-to-one correspondence with each one of the semiconductor channels; the gate dielectric layer has an L-shaped cross-section in the plane perpendicular to the third direction; and the gate is disposed on a side of the gate dielectric layer away from each one of the semiconductor channels.
11. 11 . The semiconductor structure according to claim 1 , wherein each of the bit lines comprises a first sub-bit line and a second sub-bit line which are spaced from each other in the first direction and extend in the second direction; and the semiconductor structure further comprises insulation layers each located between the first sub-bit line and the second sub-bit line.
12. 12 . The semiconductor structure according to claim 1 , wherein, a material of the semiconductor channels comprises silicon or silicon germanium.
13. 13 . The semiconductor structure according to claim 1 , further comprising capacitive structures; wherein each of the capacitive structures is at least in contact with a side of a respective semiconductor channel away from the bit lines in the third direction.
14. 14 . A manufacturing method of a semiconductor structure, comprising: forming semiconductor channels extending in a third direction, wherein each of the semiconductor channels has an L-shaped cross-section in a plane perpendicular to the third direction, each of the semiconductor channels comprises a first L-shaped sidewall and a second L-shaped sidewall which are opposite to each other and extend in the third direction, the first L-shaped sidewall comprises a first face extending in a first direction and a second face extending in a second direction; forming first gate structures and second gate structures which are in contact with each other, wherein each of the first gate structures is in contact with the first face, each of the second gate structures is in contact with the second face, and forms a combined structure together with a respective one of the second gate structures, the combined structure has an L-shaped cross-section in the plane perpendicular to the third direction; and forming bit lines extending in the second direction and located on a side of each of the semiconductor channels in the third direction; wherein the first direction, the second direction and the third direction intersect with each other.
15. 15 . The manufacturing method according to claim 14 , wherein the forming the semiconductor channels comprises: forming semiconductor columns arranged at intervals in at least one of the first direction or the second direction; and forming the semiconductor channels on sidewalls of the semiconductor columns extending in the third direction, with each of the semiconductor columns being in contact with two respective semiconductor channels, wherein the semiconductor channels are arranged in at least one of following ways: (a) every two semiconductor channels in contact with a same semiconductor column are arranged centrosymmetrically, or (b) adjacent semiconductor channels in the first direction are arranged axisymmetrically.
16. 16 . The manufacturing method according to claim 15 , wherein each of the semiconductor columns has a first side and a second side opposite to each other in the second direction, a length of each of the semiconductor columns in the second direction is a third length; after the semiconductor columns are formed and before the semiconductor channels are formed, the manufacturing method further comprises: forming third isolation layers and fourth isolation layers alternately located between adjacent semiconductor columns in the first direction, wherein one of sidewalls of each third isolation layer which extends in the third direction is flush with the first side, a length of each of the third isolation layers in the second direction is less than the third length; one of sidewalls of each fourth isolation layer which extends in the third direction is flush with the second side, a length of each of the fourth isolation layers in the second direction is less than the third length; and forming the semiconductor channels on parts of sidewalls of the semiconductor columns extending in the third direction which are exposed by the third isolation layers and the fourth isolation layers.
17. 17 . The manufacturing method according to claim 16 , wherein the semiconductor structure meets at least one of following requirements: (a) a ratio of the length of each of the third isolation layers in the second direction to the third length ranges from ½ to ⅔, or (b) a ratio of the length of each of the fourth isolation layers in the second direction to the third length ranges from ½ to ⅔.
18. 18 . The manufacturing method according to claim 16 , wherein, before the semiconductor columns are formed, the manufacturing method comprises: providing a substrate; and forming an initial insulation layer on the substrate; wherein the forming the semiconductor columns comprises: forming the semiconductor columns on a side of the initial insulation layer away from the substrate; after the semiconductor channels are formed, the forming the bit lines comprises: removing the semiconductor columns to form first grooves, and forming first isolation layers filled in the first grooves; removing the third isolation layers and the fourth isolation layers; etching the initial insulation layer through gaps provided between the adjacent semiconductor channels in the first direction, to form second grooves, wherein at least parts of bottom surfaces of the semiconductor channels facing the substrate are exposed from the second grooves, an orthographic projection of each gap on the substrate is located in an orthographic projection of a respective one of the second grooves on the substrate, remaining parts of the initial insulation layer form insulation layers; and forming the bit lines in the second grooves, with the bit lines being in contact with at least part of bottom surfaces of the semiconductor channels facing the substrate and exposed through the second groove, wherein each of the bit lines comprises a first sub-bit line and a second sub-bit line which are located respectively on two opposite sides of the respective insulation layer in the first direction, the first sub-bit lines and the second sub-bit lines extend in the second direction.
19. 19 . The manufacturing method according to claim 18 , wherein after the semiconductor channels are formed, the forming the first gate structures and the second gate structures comprises: forming second isolation layers covering parts of sidewalls of the first isolation layers extending in the third direction and exposed from the semiconductor channels, with each of the second isolation layers being connected to adjacent first isolation layers in the first direction, wherein sidewalls of the semiconductor channels and the second isolation layers which extend in the third direction together form a reference sidewall, the reference sidewall comprises a first region, a second region and a third region arranged in sequence in the third direction; and forming gate structures located in the second region, with each of the gate structures being in contact with a plurality of the semiconductor channels arranged at intervals in the first direction, wherein each of the gate structures comprises at least the first gate structure and the second gate structure.
20. 20 . The manufacturing method according to claim 14 , wherein the bit lines are formed before the semiconductor channels, the first gate structures and the second gate structures are formed, and the forming the bit lines comprises: providing a substrate and forming the bit lines on the substrate, with the bit lines extending in the second direction and being arranged at intervals in the first direction, wherein forming the semiconductor channels comprises: forming the semiconductor channels on sides of the bit lines away from the substrate, with a bottom surface of each semiconductor channel facing the substrate being in contact with a respective one of the bit lines.

Description

CROSS-REFERENCE TO RELATED APPLICATION This is a continuation application of International Patent Application No. PCT/CN2022/131127, filed on Nov. 10, 2022, which claims priority to Chinese patent application No. 202211357775.5, filed on Nov. 1, 2022 and entitled “SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME”. The disclosures of International Patent Application No. PCT/CN2022/131127 and Chinese patent application No. 202211357775.5 are incorporated by reference herein in their entireties. TECHNICAL FIELD The present disclosure relates to the field of semiconductor technologies, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure. BACKGROUND With the development of semiconductor structures, the critical dimensions of the semiconductor structures are decreasing. However, due to the restriction of lithography machines, there is a limit to the scaling down of the critical dimensions of the semiconductor structures. Therefore, the researchers and practitioners in the semiconductor field are committed to manufacturing a chip with higher storage density by a wafer. In the two-dimensional or planar semiconductor devices, the memory cells are arranged in the horizontal direction. Thus the integration density of the two-dimensional or planar semiconductor device can be determined by the area occupied by a unit memory cell, and the integration density of the two-dimensional or planar semiconductor devices is greatly influenced by the technologies of forming fine patterns, which causes the limitation to the continuous increasing of the integration density of the two-dimensional or planar semiconductor devices. Therefore, the semiconductor devices are developing towards three-dimensional semiconductor devices. However, with the increasing of the integration density of the semiconductor structure, the reduced spacing between adjacent memory cells causes that the adjacent memory cells are prone to interfere with each other, thereby leading to a deterioration of the electrical performance of the semiconductor structure. Thus it is difficult to achieve a balance between the integration density and the electrical performance of the semiconductor structure. SUMMARY According to some embodiments of the present disclosure, one aspect of the embodiments of the present disclosure provides a semiconductor structure, including: semiconductor channels extending in a third direction, first gate structures, second gate structures and bit lines. Each of the semiconductor channels has an L-shaped cross-section in a plane perpendicular to the third direction, each of the semiconductor channels includes a first L-shaped sidewall and a second L-shaped sidewall which are opposite to each other and extend in the third direction, the first L-shaped sidewall includes a first face extending in a first direction and a second face extending in a second direction. Each of the first gate structures is in contact with the first face. Each of the second gate structures is in contact with the second face. Each of the first gate structures is in contact with a respective one of the second gate structures, and forms a combined structure together with the respective one of the second gate structures. The combined structure has an L-shaped cross-section in the plane perpendicular to the third direction. The bit lines extend in the second direction and are located on a side of each of the semiconductor channels in the third direction. The first direction, the second direction and the third direction intersect with each other. According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure provides a manufacturing method for a semiconductor structure, including operations of: forming semiconductor channels extending in a third direction, in which each of the semiconductor channels has an L-shaped cross-section in a plane perpendicular to the third direction, each of the semiconductor channels includes a first L-shaped sidewall and a second L-shaped sidewall which are opposite to each other and extend in the third direction, the first L-shaped sidewall includes a first face extending in a first direction and a second face extending in a second direction; forming first gate structures and second gate structures which are in contact with each other, in which each of the first gate structure is in contact with the first face, each of the second gate structure is in contact with the second face, and forms a combined structure together with a respective one of the second gate structures, the combined structure has an L-shaped cross-section in the plane perpendicular to the third direction; and forming bit lines extending in the second direction and located on a side of each of the semiconductor channels in the third direction. The first direction, the second direction and the third direction intersect with each other. BRIEF DESCRIPTION OF TH