US-12622025-B2 - Silicon carbide transistor with channel counter-doping and pocket-doping

Abstract

A silicon carbide transistor may be formed with a channel that includes a p-doped region between n-doped source and drain regions. A counter-doped region may be formed at the top of the channel directly underneath the gate oxide. Instead of using the conventional doping levels for the p-doped region, the doping concentration may be increase to be greater than about 1e18 cm 3 . The transistor may also include pocket regions on one or both sides of the channel. The pocket regions may be formed in the counter-doped region and may extend up to the gate oxide. These improvements individually and/or in combination may increase the current in the channel of the transistor without significantly increasing the threshold voltage beyond acceptable operating limits.

Inventors

• Ashish Pal
• Pratik B. Vyas
• El Mehdi Bazizi
• Stephen Weeks
• Ludovico Megalini
• Siddarth Krishnan

Assignees

• APPLIED MATERIALS, INC.

Dates

Publication Date

20260505

Application Date

20230127

Claims (19)

1. 1 . A silicon carbide transistor comprising: a source region; a drain region; a gate oxide; and a channel region between the source region and the drain region and beneath the gate oxide, wherein the channel region comprises: a p-doped silicon carbide region that is doped at a concentration greater than about 1e18 cm 3 ; a counter-doped region comprising n-doped silicon carbide, wherein the counter-doped region is between the p-doped silicon carbide region and the gate oxide; and a first p-doped pocket region between the source region and the counter-doped region.
2. 2 . The silicon carbide transistor of claim 1 , wherein the channel region further comprises: a second p-doped pocket region between the drain region and the counter-doped region.
3. 3 . The silicon carbide transistor of claim 1 , wherein the counter-doped region is doped at a concentration that is less than about 1e18 cm 3 .
4. 4 . The silicon carbide transistor of claim 1 , wherein the channel region has a length of about 10 μm.
5. 5 . The silicon carbide transistor of claim 1 , wherein the counter-doped region and doping concentration of the p-doped silicon carbide region cause a threshold voltage of the silicon carbide transistor to increase by less than or about 3V.
6. 6 . The silicon carbide transistor of claim 1 , wherein the counter-doped region and doping concentration of the p-doped silicon carbide region cause a drive current to increase by more than or about 70%.
7. 7 . A silicon carbide transistor comprising: a source region; a drain region; a gate oxide; and a channel region between the source region and the drain region and beneath the gate oxide, wherein the channel region comprises: a p-doped silicon carbide region beneath the gate oxide; a counter-doped region comprising n-doped silicon carbide, wherein the counter-doped region is between the p-doped silicon carbide region and the gate oxide; a first p-doped pocket region between the source region and the counter-doped region; and a second p-doped pocket region between the drain region and the counter-doped region.
8. 8 . The silicon carbide transistor of claim 7 , wherein the p-doped silicon carbide region is doped at a concentration greater than about 1e18 cm 3 .
9. 9 . The silicon carbide transistor of claim 7 , wherein the first p-doped pocket region and the second p-doped pocket region contact the gate oxide.
10. 10 . The silicon carbide transistor of claim 7 , wherein the first p-doped pocket region and the second p-doped pocket region do not contact the p-doped silicon carbide region.
11. 11 . The silicon carbide transistor of claim 7 , wherein the first p-doped pocket region and the second p-doped pocket region have a vertical depth that is about half of a vertical depth of the counter-doped region.
12. 12 . The silicon carbide transistor of claim 7 , wherein the first p-doped pocket region and the second p-doped pocket region have a horizontal length of between about 0.5 nm and about 2.0 nm.
13. 13 . The silicon carbide transistor of claim 7 , wherein the first p-doped pocket region and the second p-doped pocket region have a vertical depth that is between about 0.5 μm and about 1.0 μm.
14. 14 . The silicon carbide transistor of claim 7 , wherein the first p-doped pocket region contacts the source region and the counter-doped region.
15. 15 . The silicon carbide transistor of claim 7 , wherein the second p-doped pocket region contacts the drain region and the counter-doped region.
16. 16 . A method of forming a channel region for a silicon carbide transistor, the method comprising: providing a silicon carbide layer; implanting a p-dopant in the silicon carbide layer to form a p-doped region that is doped at a concentration greater than or about 1e18 cm 3 between a source region and a drain region; implanting an n-dopant in the silicon carbide layer to form a counter-doped region comprising n-doped silicon carbide between the source region and the drain region, wherein the counter-doped region is on top of the p-doped region; and implanting a first p-doped pocket region between the source region and the counter-doped region.
17. 17 . The method of claim 16 , further comprising: implanting a second p-doped pocket region between the drain region and the counter-doped region.
18. 18 . The method of claim 17 , further comprising: determining a length and depth of the first p-doped pocket region and the second p-doped pocket region to produce a target threshold voltage shift and drive current gain.
19. 19 . The method of claim 17 , further comprising: determining a doping concentration of the first p-doped pocket region and the second p-doped pocket region to produce a target threshold voltage shift and drive current gain.

Description

TECHNICAL FIELD This disclosure generally describes channel doping for silicon carbide transistors. More specifically, this disclosure describes channel doping concentrations and/or pocket implants for improving mobility and channel current while maintaining a low threshold voltage. BACKGROUND Silicon carbide transistors offer an alternative to traditional metal-oxide-silicon field-effect transistors (MOSFETs). For example, silicon carbide transistors may be used in applications that require higher blocking voltage, lower on-state resistance, and/or higher thermal conductivity. These advantages may stem from the material advantages that are inherent in the physics of silicon carbide. Like traditional MOSFETs, silicon carbide transistors may include gate, drain, and source components that function in a similar manner. Recently, further improvements have been realized in silicon carbide transistors to improve mobility in the transistor channel. Specifically, an n-type counter-doped region in the channel may ne formed to work together with a relatively low-doped p-well. This counter-doped region causes the channel to form further away from the surface of the gate oxide to form a buried-channel device. However, while counter-doping a thin region of the channel may increase the mobility in the channel, it also dramatically increases the leakage current. Therefore, improvements in the art are needed. SUMMARY In some embodiments, a silicon carbide transistor may include a source region, a drain region, a gate oxide, and a channel region between the source region and the drain region and beneath the gate oxide. The channel region may include a p-doped silicon carbide region that is doped at a concentration greater than about 1e18 cm3. The channel region may also include a counter-doped region comprising n-doped silicon carbide, where the counter-doped region may be between the p-doped silicon carbide region and the gate oxide. In some embodiments, a silicon carbide transistor may include a source region, a drain region, a gate oxide, and a channel region between the source region and the drain region and beneath the gate oxide. The channel region may include a p-doped silicon carbide region beneath the gate oxide. The channel region may also include a counter-doped region comprising n-doped silicon carbide, where the counter-doped region may be between the p-doped silicon carbide region and the gate oxide. The channel region may also include a first p-doped pocket region between the source region and the counter-doped region, and a second p-doped pocket region between the drain region and the counter-doped region. In some embodiments, a method of forming a channel region for a silicon carbide transistor may include providing a silicon carbide layer. The method may also include implanting a p-dopant in the silicon carbide layer to form a p-doped region that is doped at a concentration greater than or about 1e18 cm3 between a source region and a drain region. The method may further include implanting an n-dopant in the silicon carbide layer to form a counter-doped region including n-doped silicon carbide between the source region and the drain region, where the counter-doped region is on top of the p-doped region. In any embodiments, any and all of the following features may be implemented in any combination and without limitation. The counter-doped region may be doped at a concentration that is less than about 1e18 cm3. The channel region may have a length of about 10 μm. The counter-doped region and doping concentration of the a p-doped silicon carbide region may cause a threshold voltage of the silicon carbide transistor to increase by less than or about 3V. The counter-doped region and doping concentration of the a p-doped silicon carbide region may cause a drive current to increase by more than or about 70%. The first p-doped pocket region and the second p-doped pocket region may contact the gate oxide. The first p-doped pocket region and the second p-doped pocket region need not contact the p-doped silicon carbide region. The first p-doped pocket region and the second p-doped pocket region may have a vertical depth that is about half of a vertical depth of the counter-doped region. The first p-doped pocket region and the second p-doped pocket region may have a horizontal length of between about 0.5 nm and about 2.0 nm. The first p-doped pocket region and the second p-doped pocket region may have a vertical depth that between about 0.5 μm and about 1.0 μm. The first p-doped pocket region may contact the source region and the counter-doped region. The second p-doped pocket region may contact the drain region and the counter-doped region. The method may also include implanting a first p-doped pocket region between the source region and the counter-doped region, and implanting a second p-doped pocket region between the drain region and the counter-doped region. The method may also include determining a length and d