US-12622026-B2 - Semiconductor device and method for manufacturing the same

US12622026B2US 12622026 B2US12622026 B2US 12622026B2US-12622026-B2

Abstract

A base layer has a low concentration peak at a position between a portion located at a same depth as a lower end portion of a gate electrode and a portion located at a same depth as an upper end portion of the gate electrode in a concentration profile of an impurity concentration in a depth direction. An impurity region has a boundary with the base layer in the depth direction at a position between a first peak position, at which the impurity concentration of the base layer is maximum between the portion located at the same depth as the lower end portion and the position of the low concentration peak, and a second peak position, at which the impurity concentration of the base layer is maximum between the position of the low concentration peak and the portion located at the same depth as the upper end portion.

Inventors

Yohei IWAHASHI
Jun Saito

Assignees

DENSO CORPORATION
TOYOTA JIDOSHA KABUSHIKI KAISHA
MIRISE Technologies Corporation

Dates

Publication Date: 20260505
Application Date: 20220929
Priority Date: 20211008

Claims (4)

1 . A semiconductor device comprising a cell region, an outer peripheral region surrounding the cell region, and a semiconductor element disposed in the cell region, the semiconductor element including: a drift layer of a first conductivity type; a base layer of a second conductivity type disposed in a surface layer portion of the drift layer; an impurity region of the first conductivity type disposed in a surface layer portion of the base layer, the impurity region having an impurity concentration higher than an impurity concentration of the drift layer; a trench gate structure including a trench penetrating the impurity region and the base layer to reach the drift layer, a gate insulating film disposed on a wall surface of the trench, and a gate electrode disposed on the gate insulating film; a high concentration layer of the first conductivity type or the second conductivity type disposed opposite from the base layer across the drift layer, the high concentration layer having an impurity concentration higher than the impurity concentration of the drift layer; a first electrode electrically connected to the base layer and the impurity region; and a second electrode electrically connected to the high concentration layer, wherein an end portion of the gate electrode located adjacent to a bottom of the trench is defined as a lower end portion, an end portion of the gate electrode located adjacent to an opening of the trench is defined as an upper end portion, and a direction in which the drift layer and the base layer are stacked is defined as a depth direction, the base layer has a concentration profile of an impurity concentration in the depth direction, and in the concentration profile, the base layer has a low concentration peak, at which the impurity concentration is minimum, at a position between a portion of the base layer located at a same depth as the lower end portion and a portion of the base layer located at a same depth as the upper end portion, a position at which the impurity concentration of the base layer is maximum between the portion of the base layer at the same depth as the lower end portion and a position of the low concentration peak is defined as a first peak position, and a position at which the impurity concentration of the base layer is maximum between the position of the low concentration peak and the portion of the base layer at the same depth as the upper end portion is defined as a second peak position, the impurity region has a boundary with the base layer in the depth direction at a position between the first peak position and the second peak position, the drift layer is also disposed in the outer peripheral region, the outer peripheral region includes a first field limiting ring (FLR) portion of the second conductivity type disposed inside the drift layer, and a second FLR portion of the second conductivity type disposed in the surface layer portion of the drift layer, each of the first FLR portion and the second FLR portion has a frame shape surrounding the cell region, the second FLR portion has a concentration profile of an impurity concentration same as the concentration profile of the impurity concentration of the base layer, and the first FLR portion has a portion facing the second FLR portion.
2 . A semiconductor device comprising a semiconductor element, the semiconductor element including: a drift layer of a first conductivity type; a base layer of a second conductivity type disposed in a surface layer portion of the drift layer; an impurity region of the first conductivity type disposed in a surface layer portion of the base layer, the impurity region having an impurity concentration higher than an impurity concentration of the drift layer; a trench gate structure including a trench penetrating the impurity region and the base layer to reach the drift layer, a gate insulating film disposed on a wall surface of the trench, and a gate electrode disposed on the gate insulating film; a high concentration layer of the first conductivity type or the second conductivity type disposed opposite from the base layer across the drift layer, the high concentration layer having an impurity concentration higher than the impurity concentration of the drift layer; a first electrode electrically connected to the base layer and the impurity region; and a second electrode electrically connected to the high concentration layer, wherein an end portion of the gate electrode located adjacent to a bottom of the trench is defined as a lower end portion, an end portion of the gate electrode located adjacent to an opening of the trench is defined as an upper end portion, and a direction in which the drift layer and the base layer are stacked is defined as a depth direction, the base layer has a concentration profile of an impurity concentration in the depth direction, and in the concentration profile, the base layer has a low concentration peak, at which the impurity concentration is minimum, at a position between a portion of the base layer located at a same depth as the lower end portion and a portion of the base layer located at a same depth as the upper end portion, a position at which the impurity concentration of the base layer is maximum between the portion of the base layer at the same depth as the lower end portion and a position of the low concentration peak is defined as a first peak position, and a position at which the impurity concentration of the base layer is maximum between the position of the low concentration peak and the portion of the base layer at the same depth as the upper end portion is defined as a second peak position, the impurity region has a boundary with the base layer in the depth direction at a position between the first peak position and the second peak position, and the impurity concentration of the base layer at the first peak position is higher than the impurity concentration of the base layer at the second peak position.
3 . The semiconductor device according to claim 1 , wherein the impurity concentration at the second peak position is higher than the impurity concentration at the first peak position.
4 . A semiconductor device comprising a semiconductor element, the semiconductor element including: a drift layer of a first conductivity type; a base layer of a second conductivity type disposed in a surface layer portion of the drift layer; an impurity region of the first conductivity type disposed in a surface layer portion of the base layer, the impurity region having an impurity concentration higher than an impurity concentration of the drift layer; a trench gate structure including a trench penetrating the impurity region and the base layer to reach the drift layer, a gate insulating film disposed on a wall surface of the trench, and a gate electrode disposed on the gate insulating film; a high concentration layer of the first conductivity type or the second conductivity type disposed opposite from the base layer across the drift layer, the high concentration layer having an impurity concentration higher than the impurity concentration of the drift layer; a first electrode electrically connected to the base layer and the impurity region; and a second electrode electrically connected to the high concentration layer, wherein an end portion of the gate electrode located adjacent to a bottom of the trench is defined as a lower end portion, an end portion of the gate electrode located adjacent to an opening of the trench is defined as an upper end portion, and a direction in which the drift layer and the base layer are stacked is defined as a depth direction, the base layer has a concentration profile of an impurity concentration in the depth direction, and in the concentration profile, the base layer has a low concentration peak, at which the impurity concentration is minimum, at a position between a portion of the base layer located at a same depth as the lower end portion and a portion of the base layer located at a same depth as the upper end portion, a position at which the impurity concentration of the base layer is maximum between the portion of the base layer at the same depth as the lower end portion and a position of the low concentration peak is defined as a first peak position, and a position at which the impurity concentration of the base layer is maximum between the position of the low concentration peak and the portion of the base layer at the same depth as the upper end portion is defined as a second peak position, the impurity region has a boundary with the base layer in the depth direction at a position between the first peak position and the second peak position, and the position of the boundary of the impurity region with the base layer in the depth direction matches a level of the position of the low concentration peak in the depth direction.

Description

CROSS REFERENCE TO RELATED APPLICATION The present application claims the benefit of priority from Japanese Patent Application No. 2021-166063 filed on Oct. 8, 2021. The entire disclosure of the above application is incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device having a trench gate structure and a manufacturing method thereof. BACKGROUND Conventionally, a semiconductor device including a semiconductor element such as a metal oxide semiconductor field effect transistor (MOSFET) has been proposed. SUMMARY The present disclosure provides a semiconductor device including a base layer, an impurity region disposed in a surface layer portion of the base layer, and a trench gate structure. The trench gate structure includes a trench penetrating the impurity region and the base layer, a gate insulating layer disposed on a wall surface of the trench, and a gate electrode disposed on the gate insulating layer. The base layer has a low concentration peak at a position between a portion located at a same depth as a lower end portion of the gate electrode and a portion located at a same depth as an upper end portion of the gate electrode in a concentration profile of an impurity concentration in a depth direction. An impurity region has a boundary with the base layer in the depth direction at a position between a first peak position, at which the impurity concentration of the base layer is maximum between the portion located at the same depth as the lower end portion and the position of the low concentration peak, and a second peak position, at which the impurity concentration of the base layer is maximum between the position of the low concentration peak and the portion located at the same depth as the upper end portion. The present disclosure also provides a manufacturing method of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS Objects, features and advantages of the present disclosure will become apparent from the following detailed description made with reference to the accompanying drawings. In the drawings: FIG. 1 is a cross-sectional view of a SiC semiconductor device according to a first embodiment; FIG. 2 is a perspective sectional view showing a cell region in FIG. 1; FIG. 3 is a diagram showing a relationship between a depth of a semiconductor substrate and an impurity concentration; FIG. 4 is a diagram for explaining an effective concentration related to a threshold voltage; FIG. 5A is a cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 1; FIG. 5B is a cross-sectional view showing a manufacturing process of the SiC semiconductor device continued from FIG. 5A; FIG. 5C is a cross-sectional view showing a manufacturing process of the SiC semiconductor device continued from FIG. 5B; FIG. 5D is a cross-sectional view showing a manufacturing process of the SiC semiconductor device continued from FIG. 5C; FIG. 5E is a cross-sectional view showing a manufacturing process of the SiC semiconductor device continued from FIG. 5D; FIG. 5F is a cross-sectional view showing a manufacturing process of the SiC semiconductor device continued from FIG. 5E; FIG. 5G is a cross-sectional view showing a manufacturing process of the SiC semiconductor device continued from FIG. 5F; FIG. 6 is a diagram showing a relationship between a depth of a semiconductor substrate and an impurity concentration in a second embodiment; and FIG. 7 is a diagram showing a relationship between a depth of a semiconductor substrate and an impurity concentration in a third embodiment. DETAILED DESCRIPTION A semiconductor device may include a semiconductor substrate having a drift layer, a base layer formed to one surface side of the semiconductor substrate, and a source region formed in a surface layer portion of the base layer. The semiconductor substrate may have a trench penetrating the source region and the base layer. A gate insulating film and a gate electrode may be disposed in the trench to form a trench gate structure. A drain region may be disposed to the other surface side of the semiconductor substrate. An upper electrode may be disposed to the one surface side of the semiconductor substrate so as to be electrically connected to the source region and the base layer. A lower electrode may be disposed to the other surface side of the semiconductor substrate so as to be electrically connected to the drain region. In the above-described semiconductor device, when a voltage equal to or higher than a threshold voltage in an insulated gate structure is applied to the gate electrode, an inversion layer (that is, a channel) is formed in a portion of the base layer in contact with the trench. Then, a current flows between the upper electrode and the lower electrode in the semiconductor device through the inversion layer. In a case where the base layer is formed so that the impurity concentration is substantially constant from the one su